參數(shù)資料
型號(hào)： PCA9621D,118
廠商： NXP Semiconductors
文件頁數(shù)： 16/18頁
文件大?。?/td> 0K
描述： IC BUS OUTPUT PORT 2WIRE 16SOIC
產(chǎn)品培訓(xùn)模塊： I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標(biāo)準(zhǔn)包裝： 1
接口： I²C 總線，SM 總線
輸入/輸出數(shù)： 8
中斷輸出： 無
頻率 - 時(shí)鐘： 1MHz
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SO
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 568-6671-6
PCA9621
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
7 of 18
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
10. Characteristics
Table 4.
Characteristics
Tamb = 40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Power supply
VDD
supply voltage
operating
2.7
-
5.5
V
IDD
supply current
quiescent; VI (RESET pin) = 0 V;
VDD =5.5 V
--
1
μA
I2C-bus ports (SCL, SDA)
VI2C-bus
I2C-bus voltage
SDA, SCL
VSS 0.3
-
VDD +0.3
V
VIL
LOW-level input voltage
VDD =2.7 V
0.4
V
VDD =5.5 V
0.5
V
VIH
HIGH-level input voltage
VDD =2.7 V
[1] 1.2
-
V
VDD =5.5 V
[1] 2.0
-
V
ILI
input leakage current
pin at VDD or VSS
1-
+1
μA
VOL
LOW-level output voltage
IOL =30 mA; VDD = 2.7 V
-
260
450
mV
IOL =30 mA; VDD = 5.5 V
-
140
275
mV
Open-drain output ports (P0 to P7)
IO(sink)
output sink current
LOW-level; port enabled
65
-
mA
VOL
LOW-level output voltage
IOL = 65 mA
-
440
725
mV
IOL =100 μA-
1
-
mV
RESET
VIH
HIGH-level input voltage
VDD = 2.7 V
2.0
-
V
VDD = 5.5 V
4.8
-
V
VIL
LOW-level input voltage
VDD = 2.7 V
-
650
mV
VDD = 5.5 V
-
900
mV
Vhys
hysteresis voltage
VDD = 2.7 V
100
-
mV
VDD = 5.5 V
200
-
mV
ILI
input leakage current
pin at VDD or VSS
1-
+1
μA
tw(rst)L
LOW-level reset time
VI <VIL
[2] -25
-
ns
trst
reset time
RESET pin; from VI > VIH
-
250
500
ns
tPOR
power-on reset pulse time
RESET pin; from VI > VIH
-
250
500
ns
Address pins (A0, A1, A2)
VIH
HIGH-level input voltage
VDD = 2.7 V
1.7
-
V
VDD = 5.5 V
3.5
-
V
VIL
LOW-level input voltage
VDD = 2.7 V
-
0.7
V
VDD = 5.5 V
-
1.5
V
ILI
input leakage current
pin at VDD or VSS
1-
+1
μA
Timing characteristics
tf
fall time of both SDA and
SCL signals
RPU = 200 Ω; measured from
70 % VDD to 30 % VDD
-16
-
ns
tv(Q)
data output valid time
-
500
ns
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