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參數(shù)資料
| 型號： | PCA9621D,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUS OUTPUT PORT 2WIRE 16SOIC |
| 產(chǎn)品培訓模塊： | I²C Bus Fundamentals |
| 特色產(chǎn)品： | NXP - I2C Interface |
| 標準包裝： | 1 |
| 接口： | I²C 總線，SM 總線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 無 |
| 頻率 - 時鐘： | 1MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SO |
| 包裝： | 標準包裝 |
| 其它名稱： | 568-6671-6 |
PCA9621
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
4 of 18
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
7.
Functional description
Refer to Figure 1 “Block diagram of PCA9621”.
7.1 VDD, VSS — DC supply pins
The power supply voltage for the PCA9621 may be any voltage in the range 2.7 V to
5.5 V. All other I/Os are clamped to VDD and VSS through ESD protection diodes.
7.2 SCL, SDA — 2-wire bus interface
The state of the output ports is determined by the Control register, which is set and read
via a 2-wire bus interface using I2C-bus style signalling. The interface is Fast-mode Plus
(Fm+) I2C-bus compatible, though the ports contain ESD protection diodes to the positive
and negative supplies. Consequently, VI2C-bus (voltage at SCL and SDA) must remain
within the VDD and VSS supply levels.
7.3 P0 to P7 — output ports
There are eight open-drain output ports whose state is determined by the Control register.
Programming a ‘1’ or HIGH to the relevant register bit will turn on the corresponding port,
resulting at a LOW or ‘0’ at the port. In the case of LED driving, this would result in the
LED turning ON.
Programming a ‘0’ or LOW in the register turns off the open-drain port, placing it in a
high-impedance mode.
The ports are protected by ESD diodes to the supplies so they must not be driven above
the VDD or below the VSS levels.
7.4 RESET — reset IC to default state
The active LOW RESET input is used to disable the buffer and reset it to its default state.
The RESET signal will clear the contents of the Control register, turning off all output
ports, and resetting the state of the I2C-bus slave transceiver block.
7.5 Power-On Reset (POR)
During power-on, the PCA9621 is internally held in the reset condition for a maximum of
trst = 500 ns. The default condition after reset is for the Control register to be erased
(all zeros), resulting in all output ports being off (high-impedance).
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