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參數(shù)資料
| 型號： | PCA9555N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit I2C and SMBus I/O port with interrupt |
| 中文描述： | 16 I/O, PIA-GENERAL PURPOSE, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015, SOT101-1, DIP-24 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大小： | 185K |
| 代理商： | PCA9555N |
Philips Semiconductors
Product data sheet
PCA9555
16-bit I
2
C and SMBus I/O port with interrupt
2004 Sep 30
6
REGISTERS
Command Byte
Command
Register
0
Input port 0
1
Input port 1
2
Output port 0
3
Output port 1
4
Polarity inversion port 0
5
Polarity inversion port 1
6
Configuration port 0
7
Configuration port 1
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Registers 0 and 1 — Input Port Registers
bit
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
IO.0
default
X
X
X
X
X
X
X
X
bit
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
default
X
X
X
X
X
X
X
X
This register is an input-only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
The default value ‘X’ is determined by the externally applied logic
level.
Registers 2 and 3 — Output Port Registers
bit
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
default
1
1
1
1
1
1
1
1
bit
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
default
1
1
1
1
1
1
1
1
This register is an output-only port. It reflects the outgoing logic
levels of the pins defined as outputs by Register 6 and 7. Bit values
in this register have no effect on pins defined as inputs. In turn,
reads from this register reflect the value that is in the flip-flop
controlling the output selection, NOT the actual pin value.
Registers 4 and 5 — Polarity Inversion Registers
bit
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
default
0
0
0
0
0
0
0
0
bit
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
default
0
0
0
0
0
0
0
0
This register allows the user to invert the polarity of the Input Port
register data. If a bit in this register is set (written with ‘1’), the Input
Port data polarity is inverted. If a bit in this register is cleared (written
with a ‘0’), the Input Port data polarity is retained.
Registers 6 and 7 — Configuration Registers
bit
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
default
1
1
1
1
1
1
1
1
bit
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
default
1
1
1
1
1
1
1
1
This register configures the directions of the I/O pins. If a bit in this
register is set (written with ‘1’), the corresponding port pin is enabled
as an input with high impedance output driver. If a bit in this register
is cleared (written with ‘0’), the corresponding port pin is enabled as
an output. Note that there is a high value resistor tied to V
DD
at each
pin. At reset the device’s ports are inputs with a pull-up to V
DD
.
POWER-ON RESET
When power is applied to V
DD
, an internal power-on reset holds the
PCA9555 in a reset condition until V
DD
has reached V
POR
. At that
point, the reset condition is released and the PCA9555 registers and
SMBus state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by
the time the power supply is above V
POR
. However, when it is
required to reset the part by lowering the power supply, it is
necessary to lower it below 0.2 V.
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