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參數(shù)資料
型號: PCA9555N,112
廠商: NXP Semiconductors
文件頁數(shù): 34/34頁
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 24DIP
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 15
接口: I²C,SM 總線
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 24-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 24-DIP
包裝: 管件
包括: POR
產(chǎn)品目錄頁面: 826 (CN2011-ZH PDF)
配用: 568-4002-ND - DEMO BOARD I2C
其它名稱: 568-2027-5
935276768112
PCA9555N
PCA9555_8
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
9 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.5 Bus transactions
6.5.1 Writing to the port registers
Data is transmitted to the PCA9555 by sending the device address and setting the least
signicant bit to a logic 0 (see Figure 8 “PCA9555 device address”). The command byte is
sent after the address and determines which register will receive the data following the
command byte.
The eight registers within the PCA9555 are congured to operate as four register pairs.
The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Conguration
Ports. After sending data to one register, the next data byte will be sent to the other
register in the pair (see Figure 10 and Figure 11). For example, if the rst byte is sent to
Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, each 8-bit register may be updated independently of the other registers.
At power-on reset, all registers return to default values.
Fig 9.
Simplied schematic of I/Os
VDD
I/O pin
output port
register data
configuration
register
DQ
CK
Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aac703
FF
data from
shift register
FF
Q1
Q2
VSS
to INT
100 k
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