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參數(shù)資料
| 型號： | PCA9546D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-channel I2C switch with reset |
| 中文描述： | 9546 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 139K |
| 代理商： | PCA9546D |
Philips Semiconductors
Product data sheet
PCA9546
4-channel I
2
C switch with reset
2004 Sep 30
5
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9546 is
shown in Figure 3. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
A1 A0
1
1
0
A2
SW00915
1
R/W
FIXED
HARDWARE SELECTABLE
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9546, which will be stored
in the control register. If multiple bytes are received by the
PCA9546, it will save the last byte received. This register can be
written and read via the I
2
C-bus.
SW01026
CHANNEL SELECTION BITS
(READ/WRITE)
6
5
4
2
1
0
7
3
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
X
X
X
X
B3
B2
B1
B0
Figure 4. Control register
CONTROL REGISTER DEFINITION
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9546 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
condition has been placed on the I
2
C-bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
D7
D6
D5
D4
B3
B2
B1
B0
COMMAND
Channel 0
disabled
Channel 0
enabled
Channel 1
disabled
Channel 1
enabled
Channel 2
disabled
Channel 2
enabled
Channel 3
disabled
Channel 3
enabled
No channel
selected;
power-up/reset
default state
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
X
1
X
X
X
X
X
0
X
X
1
X
X
X
X
0
X
X
X
1
0
0
0
0
0
0
0
0
NOTE:
Several channels can be enabled at the same time.
Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are
disabled and channel 1 and 2 are enabled.
Care should be taken not to exceed the maximum bus capacity.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of t
WL
, the PCA9546 will reset its registers and I
2
C state
machine and will deselect all channels. The RESET input must be
connected to V
DD
through a pull-up resistor.
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9546 in a reset state until V
DD
has reached V
POR
. At this
point, the reset condition is released and the PCA9546 registers and
I
2
C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
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