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參數(shù)資料
| 型號： | PCA9544D |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 113K |
| 代理商： | PCA9544D |
Philips Semiconductors
Product data
PCA9544
4-channel I
2
C multiplexer with interrupt logic
2
2002 Feb 20
853–2178 27763
FEATURES
1-of-4 bi-directional translating multiplexer
I
2
C interface logic; compatible with SMBus
4 Active Low Interrupt Inputs
Active Low Interrupt Output
3 address pins allowing up to 8 devices on the I
2
C bus
Channel selection via I
2
C bus
Power up with all multiplexer channels deselected
Low Rds
ON
switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
No glitch on power-up
Supports hot insertion
Low stand-by current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant Inputs
0 to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Package Offer:
SO20, TSSOP20
DESCRIPTION
The PCA9544 is a 1-of-4 bi-directional translating multiplexer,
controlled via the I
2
C bus. The SCL/SDA upstream pair fans out to
four SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register. Four interrupt inputs, INT0 to INT3,
one for each of the SCx/SDx downstream pairs, are provided. One
interrupt output, INT, which acts as an AND of the four interrupt
inputs, is provided.
A power-on reset function puts the registers in their default state and
initializes the I
2
C state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the V
DD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9544. This allows the use of different bus
voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts
can communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
PIN CONFIGURATION
A0
A1
A2
INT0
SD1
V
DD
SDA
SCL
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
SD0
SC0
INT1
INT
SC3
SD3
INT3
SC2
9
12
10
11
SC1
VSS
SD2
INT2
SW00373
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
1
SYMBOL
FUNCTION
A0
Address input 0
2
A1
Address input 1
3
A2
Address input 2
4
INT0
Active LOW interrupt input 0
5
SD0
Serial data 0
6
SC0
Serial clock 0
7
INT1
Active LOW interrupt input 1
8
SD1
Serial data 1
9
SC1
Serial clock 1
10
VSS
Supply ground
11
INT2
Active LOW interrupt input 2
12
SD2
Serial data 2
13
SC2
Serial clock 2
14
INT3
Active LOW interrupt input 3
15
SD3
Serial data 3
16
SC3
Serial clock 3
17
INT
Active LOW interrupt output
18
SCL
Serial clock line
19
SDA
Serial data line
20
V
DD
Supply voltage
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40 to +85
°
C
–40 to +85
°
C
ORDER CODE
DRAWING NUMBER
20-Pin Plastic SO
PCA9544D
SOT163-1
20-Pin Plastic TSSOP
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
PCA9544PW
SOT360-1
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