參數資料
型號: PCA9544D
英文描述: BUS CONTROLLER
中文描述: 總線控制器
文件頁數: 11/14頁
文件大?。?/td> 113K
代理商: PCA9544D
Philips Semiconductors
Product data
PCA9544
4-channel I
2
C multiplexer with interrupt logic
2002 Feb 20
11
AC CHARACTERISTICS
SYMBOL
PARAMETER
STANDARD-MODE
I
2
C-BUS
MIN
0
4.7
FAST-MODE I
2
C-BUS
UNIT
MAX
0.3
1
100
MIN
0
1.3
MAX
0.3
1
400
t
pd
f
SCL
t
BUF
Propagation delay from SDA to SD
n
or SCL to SC
n
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Set-up time for STOP condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
Data valid (HL)
Data valid (LH)
Data valid Acknowledge
ns
kHz
μ
s
t
HD;STA
4.0
0.6
μ
s
t
LOW
t
HIGH
t
SU;STA
t
SU;STO
t
HD;DAT
t
SU;DAT
t
R
t
F
C
b
4.7
4.0
4.7
4.0
0
2
250
3.45
1000
300
400
1.3
0.6
0.6
0.6
0
2
100
0.9
300
300
400
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
μ
s
μ
s
20 + 0.1C
b3
20 + 0.1C
b3
t
SP
50
50
ns
t
VD:DATL
t
VD:DATH
t
VD:ACK
INT
t
iv
t
ir
L
pwr
H
pwr
NOTES:
1. Pass gate propagation delay is calculated from the 20
typical R
ON
and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH
min
of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. C
b
= total capacitance of one bus line in pF.
1
1
μ
s
μ
s
μ
s
0.6
1
0.6
1
INTn to INT active valid time
INTn to INT inactive delay time
LOW level pulse width rejection or INTn inputs
HIGH level pulse width rejection or INTn inputs
10
500
4
2
1
500
4
2
μ
s
μ
s
ns
ns
t
SP
t
BUF
t
HD;STA
P
P
S
t
LOW
t
R
t
HD;DAT
t
F
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
SU00645
Figure 13. Definition of timing on the I
2
C-bus
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