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參數(shù)資料
| 型號： | PCA9543PW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2-channel I2C switch with interrupt logic and reset |
| 中文描述： | 9543 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 120K |
| 代理商： | PCA9543PW |
Philips Semiconductors
Product data sheet
PCA9543
2-channel I
2
C switch with interrupt logic and reset
2004 Oct 01
11
AC CHARACTERISTICS
SYMBOL
PARAMETER
STANDARD-MODE
I
2
C-BUS
MIN
—
0
4.7
FAST-MODE
I
2
C-BUS
MIN
—
0
1.3
UNIT
MAX
0.3
1
100
—
MAX
0.3
1
400
—
t
pd
f
SCL
t
BUF
Propagation delay from SDA to SD
n
or SCL to SC
n
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Setup time for STOP condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
Data valid (HL)
Data valid (LH)
Data valid Acknowledge
ns
kHz
μ
s
t
HD;STA
4.0
—
0.6
—
μ
s
t
LOW
t
HIGH
t
SU;STA
t
SU;STO
t
HD;DAT
t
SU;DAT
t
R
t
F
C
b
4.7
4.0
4.7
4.0
0
2
250
—
—
—
—
—
—
—
3.45
—
1000
300
400
1.3
0.6
0.6
0.6
0
2
100
—
—
—
—
0.9
—
300
300
400
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
μ
s
μ
s
20 + 0.1C
b3
20 + 0.1C
b3
—
t
SP
—
50
—
50
ns
t
VD:DATL
t
VD:DATH
t
VD:ACK
INT
—
—
—
1
—
—
—
1
μ
s
μ
s
μ
s
0.6
1
0.6
1
t
iv
t
ir
INTn to INT active valid time
—
4
—
4
μ
s
μ
s
ns
INTn to INT inactive delay time
—
2
—
2
L
pwr
H
pwr
RESET
t
WL(rst)
t
rst
t
REC:STA
NOTES:
1. Pass gate propagation delay is calculated from the 20
typical R
and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH
min
of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. C
b
= total capacitance of one bus line in pF.
LOW-level pulse width rejection or INTn inputs
1
—
1
—
HIGH-level pulse width rejection or INTn inputs
500
—
500
—
ns
Pulse width LOW reset
Reset time (SDA clear)
Recovery to Start
4
—
—
—
4
—
—
—
ns
ns
ns
500
0
500
0
t
SP
t
BUF
t
HD;STA
P
P
S
t
LOW
t
R
t
HD;DAT
t
F
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
SU00645
Figure 13. Definition of timing on the I
2
C-bus
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