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參數(shù)資料
| 型號： | PCA9542 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-channel IIC multiplexer and interrupt controller(2通道IIC多路復(fù)用器和中斷控制器) |
| 中文描述： | 2通道復(fù)用器和國際進口中斷控制器（2通道進口證多路復(fù)用器和中斷控制器） |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 74K |
| 代理商： | PCA9542 |
Philips Semiconductors
Product specification
PCA9542
2-channel I
2
C multiplexer and interrupt controller
1999 Oct 07
6
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
SW00368
DATA OUTPUT
BY RECEIVER
1
2
8
9
S
START condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
Figure 4. Acknowledgement on the I
2
C-bus
1
1
0
A2
A1 A0
slave address
fixed
hardware selectable
SW00453
1
Figure 5. Slave address
1
2
SCL
SDA
3
4
5
6
7
8
SDA
S
0
A
A
1
1
1
0
A2
A1 A0
SLAVE ADDRESS
start condition
R/W
acknowledge
from slave
acknowledge
from slave
t
pv
NEW CHANNEL
9
B0
X
B1
CONTROL REGISTER
PREVIOUS CHANNEL
INT0
P
SW00480
1
2
3
4
5
6
7
8
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INT1
B2
X
X
Figure 6. WRITE control register
SDA
S
1
A
NA
1
1
1
0
A2 A1 A0
start condition
R/W
acknowledge
from slave
X
B1
CONTROL REGISTER
P
stop condition
last byte
SW00481
SLAVE ADDRESS
no acknowledge
from master
B0
INT0
INT1
B2
X
X
Figure 7. READ control register
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCA9542A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-channel I2C-bus multiplexer and interrupt logic |
| PCA9542AD | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 2-CH I2C MUX W/INTERRUPT RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| PCA9542AD,112 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 2-CH I2C MUX RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| PCA9542AD,118 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 I2C MUX 2CH RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| PCA9542AD,118-CUT TAPE | 制造商:NXP 功能描述:PCA9542A Series 2-Channel I2C-bus Multiplexer and Interrupt Logic - SOIC - 14 |
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