- 您現在的位置：買賣IC網 > PDF目錄367809 > PCA9540PWDH (NXP SEMICONDUCTORS) 2-channel I2C multiplexer PDF資料下載
參數資料
| 型號： | PCA9540PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2-channel I2C multiplexer |
| 中文描述： | PCA9 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO8 |
| 封裝： | 3 MM, PLASTIC, SOT-505-1, TSSOP-8 |
| 文件頁數： | 7/10頁 |
| 文件大?。?/td> | 110K |
| 代理商： | PCA9540PWDH |
Philips Semiconductors
Product specification
PCA9540
2-channel I
2
C multiplexer
1999 Dec 15
7
AC CHARACTERISTICS
SYMBOL
PARAMETER
STANDARD-MODE
I
2
C-BUS
MIN
FAST-MODE
I
2
C-BUS
MIN
UNIT
MAX
0.3
1
100
–
MAX
0.3
1
400
–
t
pd
f
SCL
t
BUF
Propagation delay from SDA to SD
n
or SCL to SC
n
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time:
for CBUS compatible masters
for I
2
C-bus devices
Data set-up time
Set-up time for STOP condition
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
ns
kHz
μ
s
0
0
4.7
1.3
t
HD:STA
4.0
–
0.6
–
μ
s
t
LOW
t
HIGH
t
SU:STA
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
μ
s
μ
s
μ
s
t
HD:DAT
5.0
0
2
250
–
–
4.0
–
–
–
–
0
2
–
μ
s
μ
s
ns
ns
ns
μ
s
pF
0.9
3
–
300
300
–
400
t
SU:DAT
t
SU:STO
t
r
t
f
C
b
NOTES:
1. Pass gate propagation delay is calculated from the 20
typical R
ON
and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH
min
of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
4. A fast-mode I
2
C bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU:DAT
≥
250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t
rmax
+ t
SU:DAT
= 1000 + 250 = 1250 ns (according to the standard-mode
I
2
C-bus specification) before the SCL line is released.
5. C
b
= total capacitance of one bus line in pF.
100
4
1000
300
–
400
20 + 0.1C
b5
20 + 0.1C
b5
0.6
–
t
SP
t
BUF
t
HD;STA
P
P
S
t
LOW
t
R
t
HD;DAT
t
F
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
SU00645
Figure 8. Definition of timing on the I
2
C-bus
相關PDF資料 |
PDF描述 |
|---|---|
| PCA9540 | 2-channel I2C multiplexer |
| PCA9540D | 2-channel I2C multiplexer |
| PCA9541 | 2-to-1 I2C master selector with interrupt logic and reset |
| PCA9542 | 2-channel IIC multiplexer and interrupt controller(2通道IIC多路復用器和中斷控制器) |
| PCA9542PW | 2-channel I2C multiplexer and interrupt controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PCA9541 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C master selector with interrupt logic and reset |
| PCA9541_08 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset |
| PCA9541_09 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset |
| PCA9541A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset |
| PCA9541ABS/01 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset |
發(fā)布緊急采購，3分鐘左右您將得到回復。