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參數(shù)資料
| 型號(hào)： | PCA9540PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2-channel I2C multiplexer |
| 中文描述： | PCA9 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO8 |
| 封裝： | 3 MM, PLASTIC, SOT-505-1, TSSOP-8 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | PCA9540PWDH |
Philips Semiconductors
Product specification
PCA9540
2-channel I
2
C multiplexer
1999 Dec 15
4
CHANNEL SELECTION
A SC0x/SD0x downstream pair, or channel, is selected by the
contents of the control register. This register is written after the
PCA9540 has been addressed. The 2 LSBs of the control byte are
used to determine which channel is to be selected. When a channel
is selected, the channel will become active after a stop condition has
been placed on the I
2
C bus. This ensures that all SCx/SDx lines will
be in a HIGH state when the channel is made active, so that no
false conditions are generated at the time of connection.
CONTROL BYTE
SELECTED
CHANNEL
7
X
X
X
6
X
X
X
5
X
X
X
4
X
X
X
3
X
X
X
2
0
1
1
1
X
0
0
0
X
0
1
none
0 (SC0/SD0)
1 (SC1/SD1)
CONTROL REGISTER
X
B2
B1 B0
Channel select bits
(read/write)
X
SW00497
X
6
5
4
2
1
0
7
3
X
X
POWER-ON RESET
During power-up the control register defaults to all zeroes causing
all the channels to be deselected.
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see FIgure 1).
SDA
SCL
SW00363
data line
stable;
data valid
change
of data
allowed
Figure 1. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 2).
System configuration
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 3).
SDA
SCL
SW00365
S
P
SDA
SCL
START condition
STOP condition
Figure 2. Definition of start and stop conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
SW00366
I
2
C
MULTIPLEXER
SLAVE
Figure 3. System configuration
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| PCA9541 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C master selector with interrupt logic and reset |
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