參數(shù)資料
型號： PCA9539RPW,118
廠商： NXP Semiconductors
文件頁數(shù)： 3/37頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 16B 24TSSOP
標準包裝： 2,500
接口： I²C，SM 總線
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時鐘： 400kHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 24-TSSOP
包裝： 帶卷 (TR)
包括： POR
其它名稱： 935286605118
PCA9539RPW-T
PCA9539RPW-T-ND
PCA9539_PCA9539R
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 6 February 2013
11 of 37
NXP Semiconductors
PCA9539; PCA9539R
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.6.2 Reading the port registers
In order to read data from the PCA9539; PCA9539R, the bus master must first send the
PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see Figure 5
“PCA9539; PCA9539R device address”). The command byte is sent after the address and
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte will then be sent by the PCA9539; PCA9539R (see
Figure 9, Figure 10 and Figure 11). Data is clocked into the register on the falling edge of
the acknowledge clock pulse. After the first byte is read, additional bytes may be read but
the data will now reflect the information in the other register in the pair. For example, if you
read Input port 1, then the next byte read would be Input port 0. There is no limitation on
the number of data bytes received in one read transmission but the final byte received, the
bus master must not acknowledge the data.
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 9.
Read from register
A
S
START condition
R/W
acknowledge
from slave
002aad727
A
acknowledge
from slave
SDA
A
P
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
1101
A1 A0
1
A
1
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
COMMAND BYTE
1101
A1 A0
1
0
data from lower or
upper byte of register
LSB
MSB
DATA (last byte)
data from upper or
lower byte of register
LSB
MSB
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