參數(shù)資料
型號(hào)： PCA9535ECDTR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 0K
描述： 16-BIT I/O EXPANDER 24TSSOP
標(biāo)準(zhǔn)包裝： 2,500
接口： I²C 總線，SM 總線
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 100kHz
電源電壓： 1.65 V ~ 5.5 V
工作溫度： -55°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
包括： *
PCA9535E, PCA9535EC
http://onsemi.com
15
System Configuration
A device generating a message is a ‘transmitter’; a device
receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled
by the master are the ‘slaves’ (see Figure 16).
Figure 16. System Configuration
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2CBUS
MULTIPLEXER
SLAVE
Acknowledge
The number of data bytes transferred between the START
and the STOP conditions from transmitter to receiver is not
limited. Each 8bit byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter, whereas the master generates an extra clock
pulse for the acknowledge bit.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a master
must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The
device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, such that the SDA line
is stable LOW during the HIGH period of the acknowledge
clock pulse; setup time and hold time must be taken into
account.
A master receiver signals an end of data to the transmitter
by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event, the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
Figure 17. Acknowledgement of the I2C Bus
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
Timing and Test Setup
Figure 18. Definition of Timing on the I2C Bus
tSP
tBUF
tHD;STA
P
S
tLOW
tr
tHD;DAT
tf
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSU;STO
SDA
SCL
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