參數(shù)資料
型號(hào): PCA9512DP
廠商: NXP SEMICONDUCTORS
元件分類: 其它接口
英文描述: Level shifting hot swappable I2C and SMBus buffer
中文描述: SPECIALTY INTERFACE CIRCUIT, PDSO8
封裝: 3 MM, PLASTIC, SOT-505-1, TSSOP-8
文件頁(yè)數(shù): 4/16頁(yè)
文件大小: 176K
代理商: PCA9512DP
Philips Semiconductors
Product data sheet
PCA9512
Level shifting hot swappable I
2
C and SMBus buffer
2004 Oct 05
4
FEATURE SELECTION CHART
FEATURES
PCA9510
PCA9511
PCA9512
PCA9513
PCA9514
Idle detect
Yes
Yes
Yes
Yes
Yes
High impedance SDA, SCL pins for V
CC
= 0 V
Rise time accelerator circuitry on all SDA and SCL lines
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Rise time accelerator circuitry hardware disable pin for lightly loaded
systems
Yes
Rise time accelerator threshold 0.8 V vs 0.6 V improves noise margin
Yes
Yes
Ready open drain output
Yes
Yes
Yes
Yes
Two V
CC
pins to support 5 V to 3.3 V level translation with improved noise
margins
Yes
1 V precharge on all SDA and SCL lines
IN only
Yes
Yes
92
μ
A current source on SCLIN and SDAIN for PICMG applications
Yes
OPERATION
Start-up
When the PCA9512 is powered up either V
CC
or V
CC2
may rise first
and either may be more positive or they may can be equal, however
the PCA9512 will not leave the under voltage lock out/initialization
state until both V
CC
and V
CC2
have gone above 2.5 V. If either V
CC
or V
CC2
drops below 2.0 V it will return to the under voltage lock
out/initialization state. In the under voltage lock out state the
connection circuitry is disabled, the rise time accelerators are
disabled, and the precharge circuitry is also disabled. After both V
CC
and V
CC2
are valid, independent of which is higher, the PCA9512
enters the initialization state, during this state the 1 V precharge
circuitry is activated and pulls up the SDA and SCL pins to 1 V
through individual 100 k
nominal resistors. At the end of the
initialization state the “Stop Bit And Bus Idle” detect circuit is
enabled. When all the SDA and SCL pins have been HIGH for the
bus idle time or when all pins are HIGH and a stop condition is seen
on the SDAIN and SCLIN pins, the connect circuitry is activated,
connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1 V
precharge circuitry is disabled when the connection is made, unless
the ACC pin is LOW, the rise time accelerators are enabled at this
time also.
Connection Circuitry
Once the connection circuitry is activated, the behavior of SDAIN
and SDAOUT as well as SCLIN and SCLOUT become identical with
each acting as a bidirectional buffer that isolated the input bus
capacitance from the output bus capacitance while communicating
the logic levels. If V
CC
V
CC2
, then a level shifting function is also
performed between input and output. A LOW forced on either
SDAIN or SDAOUT will cause the other pin to be driven LOW by the
PCA9512. The same is also true for the SCL pins. Noise between
0.7V
CC
and V
CC
on the SDAIN and SCLIN pins and 0.7V
CC2
and
V
CC2
on the SDAOUT and SCLOUT pins is generally ignored
because a falling edge is only recognized when it falls below the
0.7V
CC
for SDAIN and SCLIN (or 0.7V
CC2
for SDAOUT and
SCLOUT pins) with a slew rate of at least 1.25 V/
μ
s. When a falling
edge is seen on one pin the other pin in the pair turns on a pull down
driver that is reference to a small voltage above the falling pin. The
driver will pull the pin down at a slow rate determined by the driver
and the load. The first falling pin may have a fast or slow slew rate, if
it is faster than the pull down slew rate then the initial pull down rate
will continue until it is LOW. If the first falling pin has a slow slew rate
then the second pin will be pulled down at its initial slew rate only
until it is just above the first pin voltage then they will both continue
down at the slew rate of the first. Once both sides are LOW they will
remain LOW until all the external drivers have stopped driving
LOWs. If both sides are being driven LOW to the same or nearly the
same value by external drivers, which is the case for clock
stretching and is typically the case for acknowledge, and one side
external driver stops driving, that pin will rise and rise above the
nominal offset voltage until the internal driver catches up and pulls it
back down to the offset voltage. This bounce is worst for low
capacitances and low resistances, and may become excessive.
When the last external driver stops driving a LOW, that pin will
bounce up and settle out just above the other pin as both rise
together with a slew rate determined by the internal slew rate control
and the RC time constant. As long as the slew rate is at least 1.25
V/
μ
s, when the pin voltage exceed 0.6 V the rise time accelerator
circuits are turned on and the pull down driver is turned off. If the
ACC pin is LOW the rise time accelerator circuits will be disabled
but the pull down driver will still turn off.
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PCA9513A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hot swappable I2C-bus and SMBus bus buffer
PCA9513AD 功能描述:緩沖器和線路驅(qū)動(dòng)器 HOT SWAP I2C/SMBUS BUS BUFFER RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
PCA9513AD,112 功能描述:緩沖器和線路驅(qū)動(dòng)器 HOT SWAP I2C/SMBUS RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel