參數(shù)資料
型號： PCA9512DP
廠商： NXP SEMICONDUCTORS
元件分類： 其它接口
英文描述： Level shifting hot swappable I2C and SMBus buffer
中文描述： SPECIALTY INTERFACE CIRCUIT, PDSO8
封裝： 3 MM, PLASTIC, SOT-505-1, TSSOP-8
文件頁數(shù)： 10/16頁
文件大小： 176K
代理商： PCA9512DP
Philips Semiconductors
Product data sheet
PCA9512
Level shifting hot swappable I
2
C and SMBus buffer
2004 Oct 05
10
ELECTRICAL CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V; T
amb
= –40
°
C to +85
°
C unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Power supply
V
CC
V
CC2
I
VCCI
I
VCC2
Start-up circuitry
Supply voltage
Note 1.
2.7
—
5.5
V
Card side supply voltage
Note 1.
2.7
—
5.5
V
V
CC
supply current
V
CC
supply current
V
CC
= 5.5 V; V
SDAIN
= V
SCLIN
= 0 V
V
CC
= 5.5 V; V
SDAOUT
= V
SCLOUT
= 0 V
—
1.2
3.6
mA
—
1.1
2.4
mA
V
PRE
t
EN
t
IDLE
Rise time accelerators
Precharge voltage
SDA, SCL floating; Note 1.
0.8
1.1
1.2
V
μ
s
μ
s
Enable time on power-up
Note 6.
—
180
—
Bus idle time
Notes 1 and 7.
50
140
250
I
PULLUPAC
Transient boosted pull-up current
Positive transition on SDA, SCL,
ACC = 0.7 V
×
V
; V
= 2.7 V;
Slew rate = 1.25 V/
μ
s; Note 2.
1
2
—
mA
V
ACCDIS
V
ACCEN
I
VACC
t
PDOFF
Input–output connection
Accelerator disable threshold
0.3
×
V
CC2
—
0.5
×
V
CC2
0.5
×
V
CC2
±
0.1
5
—
V
Accelerator enable threshold
0.7
×
V
CC2
1
V
μ
A
ns
A
CC
input current
A
CC
delay, on/off
–1
—
—
V
OS
Input–output offset voltage
10 k
to V
on SDA, SCL;
V
CC
= 3.3 V, V
CC2
= 3.3 V;
V
IN
= 0.2 V; Note 1; Note 3.
Guaranteed by design, not subject to
test
0
70
150
mV
f
SCL_SDA
operating frequency
0
—
400
kHz
C
IN
Digital input capacitance
Guaranteed by design,
not subject to test
—
—
10
pF
V
OL
LOW-level output voltage
Input = 0 V. SDA, SCL pins;
I
SINK
= 3 mA; V
= 2.7 V;
V
CC2
= 2.7 V; Note 1.
SDA, SCL pins = V
CC
= 5.5 V;
V
CC2
= 5.5 V
0
—
0.4
V
I
LI
Input leakage current
–1
—
5
μ
A
Timing characteristics
f
I2C
t
BUF
I
2
C operating frequency
Note 4
0
—
400
kHz
μ
s
Bus free time between stop and
start condition
Note 4
1.3
—
—
t
HD;STA
Hold time after (repeated) start
condition
Note 4
0.6
—
—
μ
s
t
SU;STA
Repeated start condition setup
time
Note 4
0.6
—
—
μ
s
t
SU;STO
t
HD;DAT
t
SU;DAT
t
LOW
t
HIGH
t
f
t
r
NOTES:
1. This specification applies over the full operating temperature range.
2. I
PULLUPAC
varies with temperature and V
CC
voltage, as shown in the Typical Performance Characteristics section.
Stop condition setup time
Note 4
0.6
—
—
μ
s
ns
Data hold time
Note 4
300
—
—
Data setup time
Note 4
100
—
—
ns
μ
s
μ
s
ns
Clock LOW period
Note 4
1.3
—
—
Clock HIGH period
Note 4
0.6
—
—
Clock, data fall time
Notes 4 and 5
20 + 0.1
×
C
B
20 + 0.1
×
C
B
—
300
Clock, data rise time
Notes 4 and 5
—
300
ns
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