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參數資料
型號: PCA9501D,112
廠商: NXP Semiconductors
文件頁數: 24/28頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 20SOIC
標準包裝: 38
接口: I²C,SM 總線
輸入/輸出數: 8
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.5 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SO
包裝: 管件
包括: EEPROM
配用: 568-4002-ND - DEMO BOARD I2C
其它名稱: 568-3353-5
935272364112
PCA9501D
PCA9501_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 February 2009
5 of 28
NXP Semiconductors
PCA9501
8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.
Functional description
7.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9501 is shown in Figure 6. Internal pull-up resistors
are incorporated on the hardware-selectable address pins.
The last bit of the address byte denes the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
Remark: Reserved I2C-bus addresses must be used with caution since they can interfere
with:
Reserved for future use I2C-bus addresses (0000 011, 1111 1xx)
Slave devices that use the 10-bit addressing scheme (1111 0xx)
Slave devices that are designed to respond to the General Call address (0000 000)
Hs-mode master code (0000 1xx)
Fig 5.
Simplied schematic diagram of each I/O
002aac001
write pulse
read pulse
D
CI
S
FF
Q
power-on reset
data from shift register
100
A
VDD
IO0 to IO7
VSS
D
CI
S
FF
Q
data to shift register
to interrupt logic
a. I/O expander
b. Memory
Fig 6.
PCA9501 slave addresses
002aac002
0
A5
A4
A3
A2
A1
A0 R/W
fixed
slave address
hardware programmable
002aac003
1
A5
A4
A3
A2
A1
A0 R/W
fixed
slave address
hardware programmable
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