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參數(shù)資料
型號(hào)： PCA9501D,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 2/28頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 8B 20SOIC
標(biāo)準(zhǔn)包裝： 38
接口： I²C，SM 總線
輸入/輸出數(shù)： 8
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2.5 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SO
包裝： 管件
包括： EEPROM
配用： 568-4002-ND - DEMO BOARD I2C
其它名稱(chēng)： 568-3353-5
935272364112
PCA9501D
PCA9501_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 10 February 2009
10 of 28
NXP Semiconductors
PCA9501
8-bit I2C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
7.4.2.2
Random read
The PCA9501’s random read mode allows the address to be read from to be specied by
the master. This is done by performing a dummy write to set the address counter to the
location to be read. The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the acknowledge from the
PCA9501, the master re-issues the START condition and memory slave address with the
R/W bit set to one. The PCA9501 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed location. The master
ceases the transmission by issuing the STOP condition after the eighth bit, omitting the
ninth clock cycle acknowledge.
7.4.2.3
Sequential read
The PCA9501 sequential read is an extension of either the current address read or
random read. If the master does not issue a STOP condition after it has received the
eighth data bit, but instead issues an acknowledge, the PCA9501 will increment the
address counter and use the next eight cycles to transmit the data from that location. The
master can continue this process to read the contents of the entire memory. Upon
reaching address 255 the counter will return to address 0 and continue transmitting data
until a STOP condition is received. The master ceases the transmission by issuing the
STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge.
Fig 14. Current address read
1
A
S
slave address (memory)
START condition
R/W
acknowledge
from slave
002aad298
data from memory
SDA
A5 A4 A3 A2 A1 A0
1
P
STOP condition
Fig 15. Random read
0
A
S
slave address (memory)
START condition
R/W
acknowledge
from slave
002aad299
word address
SDA
A5 A4 A3 A2 A1 A0
1
P
STOP
condition
A
acknowledge
from slave
data from memory
A
acknowledge
from slave
1
S
slave address (memory)
START condition
R/W
A5 A4 A3 A2 A1 A0
1
Fig 16. Sequential read
1
A
S
slave address (memory)
START condition
R/W
acknowledge
from slave
002aad300
data from memory
SDA
A5 A4 A3 A2 A1 A0
1
P
STOP
condition
A
acknowledge
from master
data from memory
DATA n
data from memory
DATA n + 1
A
acknowledge
from master
DATA n + X
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