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參數(shù)資料
型號(hào)： PCA8575PW,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 9/30頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 16B 24TSSOP
產(chǎn)品培訓(xùn)模塊： I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標(biāo)準(zhǔn)包裝： 63
接口： I²C
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
包括： POR
產(chǎn)品目錄頁(yè)面： 824 (CN2011-ZH PDF)
其它名稱： 568-4230-5
935283505112
PCA8575PW
PCA8575PW-ND
PCA8575_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 21 March 2007
17 of 30
NXP Semiconductors
PCA8575
Remote 16-bit I/O expander for I2C-bus with interrupt
13. Dynamic characteristics
[1]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undened region SCL’s falling edge.
[4]
The maximum tf for the SDA and SCL bus lines is specied at 300 ns. The maximum fall time for the SDA output stage tf is specied at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specied tf.
[5]
Cb = total capacitance of one bus line in pF.
[6]
Input lters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Table 6.
Dynamic characteristics
VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = 40 °Cto+85 °C; unless otherwise specied.
Symbol
Parameter
Conditions
Fast mode I2C-bus
Unit
Min
Typ
Max
fSCL
SCL clock frequency
0
-
400
kHz
tBUF
bus free time between a STOP and START
condition
1.3
-
s
tHD;STA
hold time (repeated) START condition
0.6
-
s
tSU;STA
set-up time for a repeated START condition
0.6
-
s
tSU;STO
set-up time for STOP condition
0.6
-
s
tHD;DAT
data hold time
0
-
ns
tVD;ACK
data valid acknowledge time
[1] 0.1
-
0.9
s
tVD;DAT
data valid time
--ns
tSU;DAT
data set-up time
100
-
ns
tLOW
LOW period of the SCL clock
1.3
-
s
tHIGH
HIGH period of the SCL clock
0.6
-
s
tf
fall time of both SDA and SCL signals
[3][4] 20 + 0.1Cb[5] -
300
ns
tr
rise time of both SDA and SCL signals
20 + 0.1Cb[5] -
300
ns
tSP
pulse width of spikes that must be suppressed
by the input lter
-
50
ns
Port timing; CL ≤ 100 pF (see Figure 11 and Figure 12)
tv(Q)
data output valid time
-
4
s
tsu(D)
data input set-up time
0
-
s
th(D)
data input hold time
4
-
s
Interrupt timing; CL ≤ 100 pF (see Figure 11 and Figure 12)
tv(D)
data input valid time
-
4
s
td(rst)
reset delay time
-
4
s
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