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參數(shù)資料
| 型號： | PC9S08QE64CLH |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 8/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 8BIT 64K FLASH 64-LQFP |
| 標準包裝： | 160 |
| 系列： | S08 |
| 核心處理器： | S08 |
| 芯體尺寸： | 8-位 |
| 速度： | 50MHz |
| 連通性： | I²C，LIN，SCI，SPI |
| 外圍設備： | LVD，PWM，WDT |
| 輸入/輸出數(shù)： | 54 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 22x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
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MC9S08QE128 Series Data Sheet, Rev. 7
Electrical Characteristics
Freescale Semiconductor
16
Figure 7. Pull-up and Pull-down Typical Resistor Values
18
P
Low-voltage detection threshold —
low range7
VLVDL
VDD falling
VDD rising
1.80
1.86
1.82
1.90
1.91
1.99
V
19
P
Low-voltage warning threshold —
high range7
VLVWH
VDD falling
VDD rising
2.36
2.46
2.56
V
20
P
Low-voltage warning threshold —
low range7
VLVWL
VDD falling
VDD rising
2.11
2.16
2.21
2.22
2.27
V
21
C
Low-voltage inhibit reset/recover
hysteresis7
Vhys
—50—
mV
22
P Bandgap Voltage Reference9
VBG
1.15
1.17
1.18
V
1 Typical values are measured at 25°C. Characterized, not tested
2 As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL.
3 All functional non-supply pins are internally clamped to VSS and VDD.
4 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).
6 Maximum is highest voltage that POR is guaranteed.
7 Low voltage detection and warning limits measured at 1 MHz bus frequency.
8 Run at 1 MHz bus frequency
9 Factory trimmed at VDD = 3.0 V, Temp = 25°C
Table 8. DC Characteristics (continued)
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
PULL-UP RESISTOR TYPICALS
VDD (V)
PULL-UP
RE
SISTO
R
(k
Ω
)
20
25
30
35
40
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
25
°C
85
°C
–40
°C
PULL-DOWN RESISTOR TYPICALS
VDD (V)
PUL
L
-D
OWN
R
E
SI
ST
ANCE
(
kΩ
)
20
25
30
35
40
1.8
2.3
2.8
3.3
25
°C
85
°C
–40
°C
3.6
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