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PC755B/745B
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Table 1. Pinout Listing for the PC745B, 255 PBGA Package
Signal Name
Notes
3.3V
1.8V/2.0V
I/O
Active
Pin Number
TT[0–4]
B13, A15, B16, C14, C15
High
I/O
—
—
WT
D2
Low
Output
—
—
VDD 2
F6, F8, F9, F11, G7, G10, H6, H8, H9,
H11, J6, J8, J9, J11, K7, K10, L6, L8,
L9, L11
—
—
2.0V
2.0V
VOLTDET
F3
High
Output
—
—
6
Notes:
1. OVdd supplies power to the processor bus, JTAG, and all control signals and Vdd supplies power to the processor core
and the PLL (after filtering to become AVDD). These columns serve as a reference for the nominal voltage supported
on a given signal as selected by the BVSEL pin configuration of Table 4 and the voltage supplied. For actual recom-
mended value of Vin or supply voltages see Table 3.
2. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.
3. To allow for future I/O voltage changes, provide the option to connect BVSEL independently to either OVDD (selects
3.3V) or to OGND (selects 1.8V/2.0V).
4. Uses one of 15 existing no-connects in PC745’s 255-bga package.
5. Internal pull up on die.
6. Internally tied to GND in the PC745B 255-bga package to indicate to the power supply that a low-voltage processor
is present. This signal is not a power supply input.
2.1.2. Pinout listing for the PC755B, 360P PBGA package.
Table 2 provides the pinout listing for the PC755B, 360 PBGA.
Table 2. Pinout Listing for the PC755B, 360 PBGA Package
I/F Voltages
Supported1
Signal Name
Pin Number
Active
I/O
1.8V/2.0V
3.3V
Notes
A[0–31]
A13, D2, H11, C1, B13, F2, C13, E5,
D13, G7, F12, G3, G6, H2, E2, L3, G5,
L4, G4, J4, H7, E1, G2, F3, J7, M3,
H3, J2, J6, K3, K2, L2
High
I/O
—
—
AACK
N3
Low
Input
—
—
ABB
L7
Low
I/O
—
—
AP[0–3]
C4, C5, C6, C7
High
I/O
—
—
ARTRY
L6
Low
I/O
—
—
AVDD
A8
—
—
2.0V
2.0V
BG
H1
Low
Input
—
—
BR
E7
Low
Output
—
—
BVSEL
W1
High
Input
GND
3.3V
3, 5, 6
CI
C2
Low
Output
—
—
CKSTP_IN
B8
Low
Input
—
—