- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367799 > PC7447VG1000N (Atmel Corp.) PowerPC 7457 RISC Microprocessor PDF資料下載
參數(shù)資料
| 型號： | PC7447VG1000N |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7457 RISC Microprocessor |
| 中文描述： | 7457的PowerPC RISC微處理器 |
| 文件頁數(shù)： | 8/66頁 |
| 文件大?。?/td> | 522K |
| 代理商： | PC7447VG1000N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
8
PC7457/47 [Preliminary]
5345B–HIREL–02/04
–
Separate instruction and data translation lookaside buffers (TLBs)
Both TLBs are 128-entry, two-way set-associative, and use LRU
replacement algorithm
TLBs are hardware- or software-reloadable (that is, on a TLB miss a page
table search is performed in hardware or by system software)
Efficient data flow
–
Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows
up to 256 bits
–
The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the
VRs
–
L2 cache is fully pipelined to provide 256 bits per processor clock cycle to
the L1 cache
–
As many as eight outstanding, out-of-order, cache misses are allowed
between the L1 data cache and L2/L3 bus
–
As many as 16 out-of-order transactions can be present on the MPX bus
–
Store merging for multiple store misses to the same line. Only coherency
action taken (address-only) for store misses merged to all 32 bytes of a
cache block (no data tenure needed)
–
Three-entry finished store queue and five-entry completed store queue
between the LSU and the L1 data cache
–
Separate additional queues for efficient buffering of outbound data (such as
castouts and write-through stores) from the L1 data cache and L2 cache
Multiprocessing support features include the following:
–
Hardware-enforced, MESI cache coherency protocols for data cache
–
Load/store with reservation instruction pair for atomic memory references,
semaphores, and other multiprocessor operations
Power and thermal management
–
1.6V processor core
–
The following three power-saving modes are available to the system:
Nap—Instruction fetching is halted. Only those clocks for the time base,
decrementer, and JTAG logic remain running. The part goes into the doze
state to snoop memory operations on the bus and then back to nap using a
QREQ/QACK processor-system handshake protocol
Sleep—Power consumption is further reduced by disabling bus snooping,
leaving only the PLL in a locked and running state. All internal functional
units are disabled
Deep sleep— When the part is in the sleep state, the system can disable the
PLL. The system can then disable the SYSCLK source for greater system
power savings. Power-on reset procedures for restarting and relocking the
PLL must be followed on exiting the deep sleep state
相關PDF資料 |
PDF描述 |
|---|---|
| PC7447VG1200L | PowerPC 7457 RISC Microprocessor |
| PC7447VG1200N | PowerPC 7457 RISC Microprocessor |
| PC7447VG933L | PowerPC 7457 RISC Microprocessor |
| PC7447VG933N | PowerPC 7457 RISC Microprocessor |
| PC7447VGH1000L | PowerPC 7457 RISC Microprocessor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PC7447VG1200L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7447VG1200N | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7447VG933L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7447VG933N | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7447VGH1000L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復。