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參數(shù)資料
| 型號： | PC7447VG1000N |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7457 RISC Microprocessor |
| 中文描述： | 7457的PowerPC RISC微處理器 |
| 文件頁數(shù)： | 25/66頁 |
| 文件大?。?/td> | 522K |
| 代理商： | PC7447VG1000N |
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25
PC7457/47 [Preliminary]
5345B–HIREL–02/04
Motorola is similarly limited by system constraints and cannot perform tests of the L3
interface on a socketed part on a functional tester at the maximum frequencies of Table
10. Therefore, functional operation and AC timing information are tested at core-to-L3
divisors which result in L3 frequencies at 250 MHz or lower.
Notes:
1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See “L3 Clock AC Specifica-
tions” on page 24 for an explanation that this maximum frequency is not functionally tested at speed by Motorola. The
minimum L3 clock frequency and period are f
SYSCLK
and t
SYSCLK
, respectively.
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals
which are common to both SRAM chips in the L3.
4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or
Late Write SRAM. This parameter is critical to the read data signals because the processor uses the feedback loop to latch
data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.
5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data and
control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the
L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage
noise or thermal effects. This is also comprehended in the AC timing specifications and need not be considered in the L3
timing analysis.
Figure 11.
L3_CLK_OUT Output Timing Diagram
Table 10.
L3_CLK Output AC Timing Specifications at Recommended Operating Conditions (see Table 3 on page 12)
Symbol
Parameter
All Speed Grades
Unit
Min
Typical
Max
f
L3_CLK
(1)
L3 clock frequency
–
200
MHz
t
L3_CLK
(1)
L3 clock cycle time
–
5
–
ns
t
CHCL
/t
L3_CLK
(2)
L3 clock duty cycle
–
50
–
%
t
L3CSKW1
(3)
L3 clock output-to-output skew (L3_CLK0 to L3_CLK1)
–
–
100
ps
t
L3CSKW2
(4)
L3 clock output-to-output skew (L3_CLK[0:1] to L3_ECHO_CLK[1:3])
–
–
100
ps
L3 clock jitter
(5)
–
–
±75
ps
L3_CLK0
VM
tL3CR
tL3CF
VM
VM
VM
L3_CLK1
VM
VM
tL3_CLK
tCHCL
VM
L3_ECHO_CLK1
L3_ECHO_CLK3
VM
VM
VM
VM
VM
VM
VM
VM
For PB2 or Late Write:
tL3CSKW1
tL3CSKW2
tL3CSKW2
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PC7447VG1200L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7447VG1200N | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7447VG933L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7447VG933N | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7447VGH1000L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
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