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參數(shù)資料
| 型號： | PC7410MGU500N |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7410 RISC Microprocessor Product Specification |
| 中文描述： | 7410的PowerPC RISC微處理器產(chǎn)品規(guī)格 |
| 文件頁數(shù)： | 5/54頁 |
| 文件大小： | 692K |
| 代理商： | PC7410MGU500N |
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5
PC7410
2141D–HIREL–02/04
–
Completion of instructions in program order while supporting out-of-order
instruction execution, completion serialization and all instruction flow
changes
Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands
–
Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
–
Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical
–
Single-cycle arithmetic, shifts, rotates, logical
–
Multiply and divide support (multi-cycle)
–
Early out multiply
Three-stage Floating-point Unit and a 32-entry FPR File
–
Support for IEEE-754 standard single- and double-precision floating-point
arithmetic
–
Three-cycle latency, one-cycle throughput (single or double precision)
–
Hardware support for divide
–
Hardware support for denormalized numbers
–
Time deterministic non-IEEE mode
System Unit
–
Executes CR logical instructions and miscellaneous system instructions
–
Special register transfer instructions
AltiVec Unit
–
Full 128-bit data paths
–
Two dispatchable units: vector permute unit and vector ALU unit
–
Contains its own 32-entry 128-bit vector register file (VRF) with six renames
–
The vector ALU unit is further sub-divided into the vector simple integer unit
(VSIU), the vector complex integer unit (VCIU) and the vector floating-point
unit (VFPU).
–
Fully pipelined
Load/Store Unit
–
One-cycle load or store cache access (byte, half-word, word, double-word)
–
Two-cycle load latency with one-cycle throughput
–
Effective address generation
–
Hits under misses (multiple outstanding misses)
–
Single-cycle unaligned access within double-word boundary
–
Alignment, zero padding, sign extend for integer register file
–
Floating-point internal format conversion (alignment, normalization)
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Sequencing for load/store multiples and string operations
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Store gathering
–
Executes the cache and TLB instructions
–
Big- and little-endian byte addressing supported
–
Misaligned little-endian supported
–
Supports FXU, FPU, and AltiVec load/store traffic
–
Complete support for all four architecture AltiVec DST streams
Level 1 (L1) Cache Structure
–
32K 32-byte line, 8-way set associative instruction cache (iL1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC7410 | PowerPC 7410 RISC Microprocessor Product Specification |
| PC7410MGHU400L | PowerPC 7410 RISC Microprocessor Product Specification |
| PC7410VGU450N | PowerPC 7410 RISC Microprocessor Product Specification |
| PC7410VGU500L | PowerPC 7410 RISC Microprocessor Product Specification |
| PC7410VGU500N | PowerPC 7410 RISC Microprocessor Product Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC7410VG400LE | 制造商:e2v technologies 功能描述:PC7410VG400LE - Trays |
| PC7410VG400NE | 制造商:e2v technologies 功能描述:PC7410VG400NE - Trays |
| PC7410VG450LE | 制造商:e2v technologies 功能描述:PC7410VG450LE - Trays |
| PC7410VG450NE | 制造商:e2v technologies 功能描述:PC7410VG450NE - Trays |
| PC7410VG500LE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 500MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
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