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參數(shù)資料
| 型號： | PC33702DWBR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 6 A SWITCHING REGULATOR, 400 kHz SWITCHING FREQ-MAX, PDSO32 |
| 封裝： | PLASTIC, SOIC-32 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 647K |
| 代理商： | PC33702DWBR2 |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
15
Figure 9. Watchdog Operation
Table 1. Watchdog Programming Command Byte
(as a 2nd Command Byte)
When the Window Watchdog function is selected, the timer
cannot be cleared during the Closed Window time, which is
50% of the total watchdog period. When the watchdog is
cleared, the timer is reset and starts a new time-out period. If
the watchdog is not cleared during the Open Window time, the
RESET
will become active (LOW) for a time determined by the
RC components of the RT timer plus 10 ms.
EN1 and EN2 Control Pins
These two pins permit positive logic control of the Enable
function and selection of the Power Sequencing mode
concurrently. Table 2 depicts the EN1 and EN2 function and
Power Sequencing mode selection.
Both EN1 and EN2 pins have internal pull-down resistors
and both can withstand a short circuit to the supply voltage,
6.0 V.
Table 2. Operating Mode Selection
Power Sequencing Modes
The power sequencing of the two outputs of this power
supply IC is in compliance with the Motorola Power QUICC and
other 32-bit microprocessor requirements. When the input
voltage is applied, the switcher and linear regulator outputs
follow the supply rail voltage during power-up and power-down
in the limits given by the microcontroller power sequencing
specification, illustrated in Figures 10 through 12. There are two
possible power sequencing modes, Standard and Inverted, as
explained in more detail below. The third mode of operation is
Power Sequencing Disabled.
Figure 10. Standard Power Up/Down Sequence
in +3.3 V Supply System
Figure 11. Standard Power Up/Down Sequence
in +5.0 V Supply System
Address
Value
Action
011
000
00
1st Command
011
000
00
WD OFF
0
1
0
1
0
WD 1280 ms
WinOFF
0
1
0
1
0
1
WD 320 ms
WinOFF
011
010
10
WD 80 ms
WinOFF
011
010
11
WD 20 ms
WinOFF
0
1
0
1
0
WD 1280 ms
WinON
0
1
0
1
0
1
WD 320 ms
WinON
011
10
WD 80 ms
WinON
011
11
WD 20 ms
WinON
Notes
12.
The Watchdog feature will be turned
ON automatically after receiving any
other valid command byte changing
watchdog time.
50% of Watchdog Period
Watchdog Period
Timing Selected via 12C Bus – See Table 1
Watchdog Closed
No Watchdog Clear Allowed
Window Open
for Watchdog Clear
Window Open for Watchdog Clear
Watchdog Period
Timing Selected via I2C Bus – See Table 1
Window Watchdog
Time-Out Watchdog
EN1
EN2
Operating Mode
0
Regulators Disabled
0
1
Standard Power Sequencing
1
0
Inverted Power Sequencing
1
Regulators Enabled,
No Power Sequencing
V = 2.0 V
Max. Lead
V = 0.4 V
Max. Lag
V = 2.0 V
Max. Lead
Slope
1.0 V/ms
(typ.)
V Start-Up
3.3 V Input Supply (I/O Voltage)
1.8 V Core Voltage
V = 2.0 V
Max. Lead
V = 0.4 V
Max. Lag
V = 0.4 V
Max. Lag
V Start-Up
3.3 V I/O Voltage (VLDO)
1.8 V Core Voltage
(VOUT)
5.0 V Input Supply
V = 2.0 V
Max. Lead
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