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參數(shù)資料
| 型號(hào)： | PC33702DWBR2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | 6 A SWITCHING REGULATOR, 400 kHz SWITCHING FREQ-MAX, PDSO32 |
| 封裝： | PLASTIC, SOIC-32 |
| 文件頁(yè)數(shù)： | 11/24頁(yè) |
| 文件大?。?/td> | 647K |
| 代理商： | PC33702DWBR2 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
19
I2C BUS OPERATION
Introduction
The 33702 device is compatible with the I2C interface
standard. SDA and SCL pins are the Serial Data and Serial
Clock pins of the I2C bus.
I2C Command and Data Formats
Communication Start
Communication starts with a START condition, followed by
the slave device unique address. Figure 13 illustrates the data
transfer beginning an I2C communication for a 7-bit slave
address.
Figure 13. Communication Using 7-Bit Address
Slave Address Definition
33702 has the two LSB’s address bits defined by the state of
the CLKSEL pin and the ADDR pin.
Note The state of the CLKSEL pin also defines the
configuration of the oscillator synchronization CLKSYN pin.
This feature allows up to four 33702 ICs to communicate in
the same I2C bus, all of them sharing the same high-order
address bits. A different combination of bits A1 and A0 is
assigned to each individual part to assure its unique address.
Figure 14 illustrates the flexible addressing feature for a 7-bit
address. Table 3 provides the definition of the selectable
portion of the device address.
Figure 14. Address Bit Definition for 7-Bit Address
Writing Data Into the Slave Device
After the address acknowledgment by the slave, DATA can
be written into the slave registers. The R/W bit must be set to 0
so DATA will be read. Figure 15 shows the data write
sequence. Actions performed by the slave device are grayed.
Figure 15. Data Transfer for Write Operations
Data Definition
For the sake of 33702 acting as a slave device, the master
writes a Command Byte and writes one Data Byte. The
Command Byte identifies the kind of operation required by the
master and has two fields, as illustrated in Figure 16:
1. Address field
2. Value field
The address field is selected from the list in Table 4.
Figure 16. Command Byte
Table 4. Address Field Definitions
Refer to Table 5, page 20, which summarizes the value field
definitions for the entire set of operation options.
S
7-Bit Address
R/W
Ack
1 0
2
3
4
5
6
1 110 1A1 A0
Bits
Fixed Address Selectable
Address
Table 3. Definition of Selectable Portion of Device Address
CLKSEL Pin
ADDR Pin
A1
A0
Low
0
Low
Open
0
1
Open
Low
1
0
Open
1
Code
Operation
Write
001
Voltage Margining
W
010
Not Used
–
011
Watchdog
W
S
7-Bit Address
0Ack
DATA
Ack
D6 D5 D4 D3
D1 D0
Bits
Address Field
Value Field
7
D7
D2
32 1
0
4
5
6
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