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| 型號(hào)： | PC33394FC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.2 A SWITCHING CONTROLLER, 220 kHz SWITCHING FREQ-MAX, PQCC44 |
| 封裝： | PLASTIC, QFN-44 |
| 文件頁數(shù)： | 26/51頁 |
| 文件大?。?/td> | 543K |
| 代理商： | PC33394FC |
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33394
32
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Table 2.
Part number
(Figure 18)
Application diagram
part number (Figure 1)
Component value
R1
33394 internal resistor
39.6k
R2
100k
R3
R1
430
C1
C6
100pF
C2
C7
1.0nF
C3
C5
3.3nF
5.3. Selecting Pull–Up Resistors
All the Resets (/PORESET, /PRERESET and /HRESET)
are open drain outputs, which can sink a maximum of 1 mA
drain current. This determines the pull–up resistor minimum
value. VKAM should be used as the pull–up source for the
/PORESET output. /PORESET is pulled low only during
initial battery connect or when VKAM is below 2.5 volts (for
VDDL = 2.6 V).
To select the /PRERESET and /HRESET pull–up resistor
connections, consider current draw during sleep modes. For
example, the pull up resistor on /PRERESET and /HRESET
should receive its source from VDDL, if the sleep mode or low
power mode of the module is initiated primarily by the state of
the VIGN pin. Refer to Figure 20 for recommended pull–up
resistor values.
Another way to connect the /PRERESET and /HRESET
pull–up resistors is to connect them to the VKAM output
together with the /PORESET pull–up resistor (see Figure 1).
This is the preferable solution when the sleep or low power
mode is initiated primarily by the microprocessor. In that
case, when the 33394 is shut down by pulling the /SLEEP pin
down, all three Resets (/PORESET, /PRERESET and
/HRESET) stay high. Since they are pulled–up to the supply
voltage (VKAM) they draw no current from the VKAM and the
module quiescent current is minimized.
5.4. Selecting Hardware Reset Timer Components
The HRT input sets the delay time from VDDH, VDD3_3
and VDDL stable to the release of /PRERESET and
/HRESET. When sizing the delay time the module design
engineer must consider capacitor leakage, printed board
leakage and HRT pin leakage. Resistor selection should be
low enough to make the leakage currents negligible. The
Hardware Reset (/HRESET) delay can be calculated as
follows:
Delay time:
tD +* RC
ln[
(VB * VSAT) * Vth
(VB * VSAT)
]
Where R is the HRT timer pull–up resistor,
C is the HRT timer capacitor
VB is the pull–up voltage,
Vth is the HRT timer threshold voltage (Vth = 2.5V
nominal value),
VSAT is the saturation voltage of the internal pull–down
transistor.
If the HRT timer pull–up resistor is connected to VDDH
(see Figure 1) and the resistor value is
≥ 47 kW, therefore the
VSAT can be neglected, the formula for calculating the time
delay can be simplified to:
tD + 0.7
RC
5.5. Selecting the VKAM Resistor Divider
The VKAM linear regulator output voltage is divided by an
external resistor divider and compared with the bandgap
reference voltage (Vbg) in the input of the VKAM error
amplifier. The resistor divider can be designed according to
the following formula:
VKAM + VKAMref
1
)
Rupper
Rlower
VKAMref = 1.267 V
Where VKAMref is the bandgap reference voltage.
Since the VKAM feedback pin (VKAM_FB) input current is
only a few nA, the resistor value can be selected sufficiently
high in order to minimize the quiescent current of the module.
See Figure 20 for the VKAM resistor divider recommended
values.
5.6. Selecting the VDDL Resistor Divider
The VDDL regulator resistor divider is designed according
to the same formula as described in the paragraph above
(see Figure 20).
VDDL + VDDLref
1
)
Rupper
Rlower
Where VDDLref = 1.267 V
Nonetheless, the actual resistor values should be chosen
several decades lower than in the previous example. This is
due to the fact that the VDDL linear regulator needs to be
pre–loaded by a minimum of 10 mA current in order to
guarantee stable operation. See Figure 20 for the VDDL
resistor divider recommended values.
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