- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369948 > PC28F128J3A-125 (Intel Corp.) Intel StrataFlash Memory (J3) PDF資料下載
參數(shù)資料
| 型號： | PC28F128J3A-125 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲器（J3） |
| 文件頁數(shù)： | 47/72頁 |
| 文件大?。?/td> | 905K |
| 代理商： | PC28F128J3A-125 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
256-Mbit J3 (x8/x16)
Datasheet
47
This two-step sequence of setup followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in SR.4 and
SR.5 being set. Also, a reliable clear block lock-bits operation can only occur when V
CC
and V
PEN
are valid. If a clear block lock-bits operation is attempted while V
PEN
≤
V
PENLK
, SR.3 and SR.5
will be set.
If a clear block lock-bits operation is aborted due to V
PEN
or V
CC
transitioning out of valid range,
block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required
to initialize block lock-bit contents to known values.
13.3
Protection Register Program
The Intel StrataFlash
memory (J3) includes a 128-bit Protection Register (PR) that can be used to
increase the security of a system design. For example, the number contained in the PR can be used
to “mate” the flash component with other system components such as the CPU or ASIC, preventing
device substitution.
The 128-bits of the PR are divided into two 64-bit segments. One of the segments is programmed at
the Intel factory with a unique 64-bit number, which is unalterable. The other segment is left blank
for customer designers to program as desired. Once the customer segment is programmed, it can be
locked to prevent further programming.
13.3.1
Reading the Protection Register
The Protection Register is read in the identification read mode. The device is switched to this mode
by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses
shown in
Table 8
or
Table 21
retrieve the specified information. To return to read array mode, write
the Read Array command (0xFF).
13.3.2
Programming the Protection Register
Protection Register bits are programmed using the two-cycle Protection Program command. The
64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time
for byte-wide configuration. First write the Protection Program Setup command, 0xC0. The next
write to the device will latch in address and data and program the specified location. The allowable
addresses are shown in
Table 8
or
Table 21
. See
Figure 26, “Protection Register Programming
Flowchart” on page 67
Any attempt to address Protection Program commands outside the defined PR address space will
result in a Status Register error (SR.4 will be set). Attempting to program a locked PR segment will
result in a Status Register error (SR.4 and SR.1 will be set).
13.3.3
Locking the Protection Register
The user-programmable segment of the Protection Register is lockable by programming Bit 1 of
the PLR to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique
device number. Bit 1 is set using the Protection Program command to program “0xFFFD” to the
PLR. After these bits have been programmed, no further changes can be made to the values stored
in the Protection Register. Protection Program commands to a locked section will result in a Status
Register error (SR.4 and SR.1 will be set). PR lockout state is not reversible.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC28F256J3C-110 | Intel StrataFlash Memory (J3) |
| PC28F128J3C-110 | Intel StrataFlash Memory (J3) |
| PC28F640J3C-110 | Intel StrataFlash Memory (J3) |
| PC28F320J3C-110 | Intel StrataFlash Memory (J3) |
| PC28F320J3A-110 | Intel StrataFlash Memory (J3) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC28F128J3A-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F128J3C-110 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F128J3C-115 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F128J3C120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash?? Memory |
| PC28F128J3C-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。