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參數(shù)資料
| 型號： | PC28F128J3A-110 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲器（J3） |
| 文件頁數(shù)： | 38/72頁 |
| 文件大?。?/td> | 905K |
| 代理商： | PC28F128J3A-110 |
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256-Mbit J3 (x8/x16)
38
Datasheet
To perform a page mode read after any other operation, the Read Array command must be issued to
read from the flash array. Asynchronous page mode reads are permitted in all blocks and are used
to access register information. During register access, only one word is loaded into the page buffer.
10.1.2
Enhanced Configuration Register (ECR)
The Enhanced Configuration Register (ECR) is a volatile storage register that when addressed to
by the Set Enhanced Configuration Register command, and can select between Four-Word Page
mode and Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when
RP# is deasserted or power is removed from the device. To modify ECR settings, use the Set
Enhanced Configuration Register command. The Set Enhanced Configuration Register command
is written along with the configuration register value, which is placed on the lower 16 bits of the
address bus A[15:0]. This is followed by a second write that confirms the operation and again
presents the enhanced configuration register data on the address bus. After executing this
command, the device returns to Read Array mode. The ECR is shown in
Table 15, “Enhanced
Configuration Register” on page 38
.
Note:
For forward compatibility reasons, if the 8-word Asynchronous Page mode is to be used on J3C, a
Clear Status Register command must be issued after issuing the Set Enhanced Configuration
Register command. See
Table 16, “J3C Asynchronous 8-Word Page Mode Command Bus-Cycle
Definition” on page 38
for further details.
NOTE:
Any reserved bits should be set to 0.
NOTE:
X = Any valid address within the device. ECD = Enhanced Configuration Register Data.
Table 15. Enhanced Configuration Register
Res.
Reserved
R
R
8W
R
R
R
R
R
R
R
R
R
R
R
R
R
ECR
.15
ECR
.14
ECR
.13
ECR
.12
ECR
.11
ECR
.10
ECR
.9
ECR
.8
ECR
.7
ECR
.6
ECR
.5
ECR
.4
ECR
.3
ECR
.2
ECR
.1
ECR
.0
BITS
DESCRIPTION
NOTES
ECR[15:14]
Reserved
Reserved for Future Use. Set to 0 until further
notice.
ECR[13]
“1” = 8Word Page mode
“0” = 4Word Page mode
ECR[12:0]
Reserved
Reserved for Future Use. Set to 0 until further
notice.
Table 16. J3C Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
Command
Bus
Cycles
Req’d.
First Bus Cycle
Second Bus Cycle
Third Bus Cycle
Oper
Addr
(1)
Data
Oper
Addr
(1)
Data
Oper
Addr
(1)
Data
Set Enhanced
Configuration Register
(Set ECR)
3
Write
ECD
0x60
Write
ECD
0x04
Write
X
0x50
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相關(guān)代理商/技術(shù)參數(shù) |
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| PC28F128J3A-115 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F128J3A-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F128J3A-125 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F128J3A-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F128J3C-110 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
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