- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98050 > PC13892BJVK (FREESCALE SEMICONDUCTOR INC) 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 PDF資料下載
參數(shù)資料
| 型號： | PC13892BJVK |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MO-195AD, MABGA-139 |
| 文件頁數(shù)： | 28/67頁 |
| 文件大?。?/td> | 2571K |
| 代理商： | PC13892BJVK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁
Analog Integrated Circuit Device Data
34
Freescale Semiconductor
13892
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages.
IC CORE
VCORE
Regulated supply output for the IC analog core circuitry. It
is used to define the PUMS VIH level during initialization. The
bandgap and the rest of the core circuitry are supplied from
VCORE. Place a 2.2
μF capacitor from this pin to
GNDCORE.
VCOREDIG
Regulated supply output for the IC digital core circuitry. No
external DC loading is allowed on VCOREDIG. VCOREDIG
is kept powered as long as there is a valid supply and/or coin
cell. Place a 2.2
μF capacitor from this pin to GNDCORE.
REFCORE
Main bandgap reference. All regulators use the main
bandgap as the reference. The main bandgap is bypassed
with a capacitor at REFCORE. No external DC loading is
allowed on REFCORE. Place a 100 nF capacitor from this pin
to GNDCORE.
GNDCORE
Ground for the IC core circuitry.
POWER GATING
PWGTDRV1 AND PWGTDRV2
Power Gate Drivers.
PWGTDRV1 is provided for power gating peripheral loads
sharing the processor core supply domain(s) SW1, and/or
SW2, and/or SW3. In addition, PWGTDRV2 provides support
to power gate peripheral loads on the SW4 supply domain.
In typical applications, SW1, SW2, and SW3 will both be
kept active for the processor modules in state retention, and
SW4 retained for the external memory in self refresh mode.
SW1, SW2, and SW3 power gating FET drive would typically
be connected to PWGTDRV1 (for parallel NMOS switches).
SW4 power gating FET drive would typically be connected to
PWGTDRV2. When low power Off mode is activated, the
power gate drive circuitry will be disabled, turning off the
NMOS power gate switches to isolate the maintained supply
domains from any peripheral loading.
SWITCHERS
SW1IN, SW2IN, SW3IN AND SW4IN
Switchers 1, 2, 3, and 4 input. Connect these pins to BP to
supply Switchers 1, 2, 3, and 4.
SW1FB, SW2FB, SW3FB AND SW4FB
Switchers 1, 2, 3, and 4 feedback. Switchers 1, 2, 3, and 4
output voltage sense respectively. Connect these pins to the
farther point of each of their respective SWxOUT pin, in order
to sense and maintain voltage stability.
SW1OUT
Switcher 1 output. Buck switcher for processor core(s).
GNDSW1
Ground for Switcher 1.
SW2OUT
Switcher 2 output. Buck switcher for processor SOG, etc.
GNDSW2
Ground for Switcher 2.
SW3OUT
Switcher 3 output. Buck switcher for internal processor
memory and peripherals.
GNDSW3
Ground for switcher 3.
SW4OUT
Switcher 4 output. Buck switcher for external memory and
peripherals.
GNDSW4
Ground for switcher 4.
DVS1 AND DVS2
Switcher 1 and 2 DVS input pins. Provided for pin
controlled DVS on the buck switchers targeted for processor
core supplies. The DVS pins may be reconfigured for
Switcher Increment / Decrement (SID) mode control. When
transitioning from one voltage to another, the output voltage
slope is controlled in steps of 25 mV per time step. These
pins must be set high in order for the DVS feature to be
enabled for each of switchers 1 or 2, or low to disable it.
SWBSTIN
Switcher BST input. The 2.2
μH switcher BST inductor
must be connected here.
SWBSTOUT
Power supply for gate driver for the internal power NMOS
that charges SWBST inductor. It must be connected to BP.
SWBSTFB
Switcher BST feedback. When SWBST is configured to
supply the UVBUS pin in OTG mode the feedback will be
switched to sense the UVBUS pin instead of the SWBSTFB
pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC13892AJVK | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 |
| PC13892BJVL | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
| PC13892BJVLR2 | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
| PC14568ED/R2 | SPECIALTY ANALOG CIRCUIT, PDIP16 |
| PC33099DW | SPECIALTY ANALOG CIRCUIT, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC13892BJVL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Trays |
| PC13892JVK | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Bulk |
| PC13892JVK/R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Power Management and User Interface IC |
| PC13892JVKR2 | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Tape and Reel |
| PC13892JVL | 制造商:Freescale Semiconductor 功能描述: 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。