參數(shù)資料
型號(hào)： PBL38773/1SO
廠商： INFINEON TECHNOLOGIES AG
元件分類： 模擬傳輸電路
英文描述： TELECOM-SLIC, PDSO28
封裝： PLASTIC, SOIC-28
文件頁(yè)數(shù)： 42/64頁(yè)
文件大?。?/td> 1052K
代理商： PBL38773/1SO
Ringing FlexiSLIC
PBL 38773/1
Ringing Voltage
Data Sheet
47
DS1, 2003-06-18
7.1
Calculation of the Input Signal
The VR input has to be connected to a signal generator or via impedance in all states.
The following equations are valid for ring load between 0.25 and 5 REN. The optimal
signal at VR pin is calculated as follows:
[17]
where:
Example:
V
BAT = 80 V, this will give VRPK = 0.81 Vpeak
With DC-offset:
[18]
[19]
where:
Example:
V
BAT = -80 V, VRDCT-R = 10 V
This will give:
VR
DC = 0.096 V and VRPK+DC = 0.714 Vpeak
7.2
Calculation of the Ring-Trip Threshold
The equations are only valid for sinusoidal waveforms with a frequency of 16-30 Hz
applied to a REN load. It is important to take into account that when using other
waveforms, frequencies or loads, peak line current can exceed the calculated I
LTHpeak..
In these cases, replace the calculated I
LTHpeak., in the equations, with the actual peak line
VR
PK
Is the peak value at the VR pin.
V
BAT
Is the voltage of the VBAT pin.
VR
DC
Is the positive DC offset in respect to GND at VR pin.
VR
DCT-R
Is the DC voltage difference between the TIP and RING wires.
VR
PK+DC
is the peak value of the AC-signal to be superimposed to the DC-voltage
VR
DC
VR
PK
V
BAT
3.5
–
94.4
-----------------------------
=
VR
DC
VRDCT R
–
103.8
------------------------
=
VR
PK
DC
+
V
BAT
3.5
–
94.4
-----------------------------
VR
DC
–
=
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