參數(shù)資料
型號(hào)： PALLV16V8-10JC
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
中文描述： EE PLD, 10 ns, PQCC20
封裝： PLASTIC, LCC-20
文件頁(yè)數(shù)： 8/22頁(yè)
文件大?。?/td> 425K
代理商： PALLV16V8-10JC
8
PALLV16V8-10 and PALLV16V8Z-20 Families
Quality and Testability
The PALLV16V8 offers a very high level of built-in quality. The erasability if the device provides a
direct means of verifying performance of all the AC and DC parameters. In addition, this verifies
complete programmability and functionality of the device to yield the highest programming yields
and post-programming function yields in the industry.
Technology
The high-speed PALLV16V8Z is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven EE cells. This technology provides strong
input-clamp diodes and a grounded substrate for clean switching.
Zero-Standby Power Mode
The PALLV16V8 features a zero-standby power mode. When none of the inputs switch for an
extended period (typically 50 ns), the PALLV16V8Z will go into standby mode, shutting down most
of its internal circuitry. The current will go to almost zero (I
CC
< 30
μ
A). The outputs will maintain
the states held before the device went into the standby mode. There is no speed penalty associated
with coming out of standby mode.
When any input switches, the internal circuitry is fully enabled, and power consumption returns
to normal. This feature results in considerable power savings for operation at low to medium
frequencies. This saving is illustrated in the I
CC
vs. frequency graph.
The PALLV16V8Z-20 has the free-running-clock feature. This means that if one or more registers
are used, switching only the CLK will not wake up the logic array or any macrocell. The device
will not be in standby mode because the CLK buffer will draw some current, but dynamic I
CC
will
typically be less than 2 mA.
Product-Term Disable
On a programmed PALLV16V8Z, any product terms that are not used are disabled. Power is cut off
from these product terms so that they do not draw current. As shown in the I
CC
vs. frequency
graph, product-term disabling results in considerable power savings. This saving is greater at the
higher frequencies.
Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zero-Power PLDs
.
相關(guān)PDF資料
PDF描述
PALLV16V8-10PC Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
PALLV16V8-10SC Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
PAN4820 On-board type DC Noise Filter for Telecom
PAQ65D48 Dual output DC-DC power module for TELECOM
PAQ65D48-3325 Dual output DC-DC power module for TELECOM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PALLV16V8-10PC 制造商:Rochester Electronics LLC 功能描述:- Bulk
PALLV16V8-10SC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
PALLV16V8Z-20JI 制造商: 功能描述: 制造商:undefined 功能描述:
PALLV16V8Z-20PI 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:Simple E2PLD, Programmable Array Logic, 20 Pin, Plastic, DIP 制造商:Lattice Semiconductor Corporation 功能描述:
PALLV16V8Z-20SI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD
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