參數(shù)資料
型號: PALLV16V8-10JC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
中文描述: EE PLD, 10 ns, PQCC20
封裝: PLASTIC, LCC-20
文件頁數(shù): 12/22頁
文件大小: 425K
代理商: PALLV16V8-10JC
12
PALLV16V8-10 (Com’l)
CAPACITANCE
1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
frequency may be affected.
3. t
CF
is a calculated value and is not guaranteed. t
CF
can be found using the following equation:
t
CF
= 1/f
MAX
(internal feedback) - tS.
Parameter
Symbol
Parameter Description
Test Condition
Typ
Unit
C
IN
Input Capacitance
V
IN
= 2.0 V
V
CC
- 3.3 V T
A
= 25°C,
f = 1 MHz
5
pF
C
OUT
Output Capacitance
V
OUT
= 2.0 V
8
pF
Parameter
Symbol
Parameter Description
-10
Unit
Min
Max
t
PD
Input or Feedback to Combinatorial Output (Note 2)
10
ns
t
S
Setup Time fromInput or Feedback to Clock
7
ns
t
H
Hold Time
0
ns
t
CO
Clock to Output
7
ns
t
WL
Clock Wdth
LOW
6
ns
t
WH
HIGH
6
ns
f
MAX
MaximumFrequency
(Notes 2 and 3)
External Feedback
1/(t
S
+ t
CO
)
71.4
MHz
Internal Feedback (fCNT
1/(t
S
+ t
CF
)
83.3
MHz
No Feedback
1/(t
S
+ t
H
)
83.3
MHz
t
PZX
OE to Output Enable
10
ns
t
PXZ
OE to Output Disable
10
ns
t
EA
Input to Output Enable Using Product TermControl
12
ns
t
ER
Input to Output Disable Using Product TermControl
12
ns
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