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參數(shù)資料
| 型號： | PALCE610H-25PC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | USE GAL DEVICES FOR NEW DESIGNS |
| 中文描述： | EE PLD, 25 ns, PDIP24 |
| 封裝： | 0.300 INCH, SKINNY, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 136K |
| 代理商： | PALCE610H-25PC |
2-379
PALCE610 Family
S-R Flip-Flop
The 8 product terms are divided between the S and R
inputs. N product terms go to the S input and 8-N prod-
uct terms go to the R input, where N can range from 0 to
8. Both the S and R inputs to the flip-flop have polarity
control via exclusive-OR gates. The S-R flip-flop opera-
tion is shown below.
SR
Q
n
Q
n+1
000
0
001
1
010
0
011
0
100
1
101
1
Not Allowed
Asynchronous Reset
All flip-flops have an asynchronous-reset product-term
input. When the product term is true, the flip-flop will re-
set to a logic LOW, regardless of the clock and data
inputs.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable sys-
tem initialization. Outputs of the PALCE610 depend on
whether they are selected as registered or combinato-
rial. If registered is selected, the output will be LOW. If
combinatorial is selected, the output will be a function of
the logic. The VCC rise must be monotonic and the reset
delay time is 1000 ns maximum.
Register Preload
The register on the PALCE610 can be preloaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct load-
ing of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.
Security Bit
After programming and verification, a PALCE610 de-
sign can be secured by programming the security bit.
Once programmed, this bit defeats readback of the in-
ternal programmed pattern by a device programmer, se-
curing proprietary designs from competitors. However,
programming and verification are also defeated by the
security bit. The bit can only be erased in conjunction
with the array during the erase cycle. Preload is not af-
fected by the security bit.
Technology
The PALCE610 is manufactured using our ad-
vanced Electrically Erasable (EE) CMOS process. This
technology uses an EE cell to replace the fuse link in bi-
polar parts, and allows Lattice to offer lower-power parts
of high complexity. In addition, since the EE cells can be
erased and reprogrammed, these devices can be 100%
factory tested before being shipped to the customer. In-
puts and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clear switching.
Programming and Erasing
The PALCE610 can be programmed on standard logic
programmers. It also may be erased to reset a previ-
ously configured device back to its virgin state. Bulk
erase is automatically performed by the programming
hardware. No special erase operation is required.
CMOS Compatibility
The PALCE610 has CMOS-compatible outputs. The
output voltage (VOH) is 3.85 V at –2.0 mA.
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