- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369946 > PALCE22V10 (Cypress Semiconductor Corp.) Flash Erasable,Reprogrammable CMOS PAL Device(可擦除閃速，CMOS可重編程PAL器件) PDF資料下載
參數(shù)資料
| 型號： | PALCE22V10 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | PAL |
| 英文描述： | Flash Erasable,Reprogrammable CMOS PAL Device(可擦除閃速，CMOS可重編程PAL器件) |
| 中文描述： | 閃光可擦除，可再編程的CMOS PAL制式設(shè)備（可擦除閃速，可重編程的CMOS器件PAL制式） |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 222K |
| 代理商： | PALCE22V10 |
PALCE22V10
6
]
Commercial Switching Characteristics PALCE22V10
[2,7]
Description
22V10-5
Min.
3
22V10-7
Min.
3
22V10-10
Min.
3
22V10-15
Min.
3
22V10-25
Min.
3
Parameter
t
PD
Max.
5
Max.
7.5
Max.
10
Max.
15
Max.
25
Unit
ns
Input to Output
Propagation Delay
[8]
Input to Output
Enable Delay
[9]
Input to Output
Disable Delay
[10]
Clock to Output Delay
[8]
Input or Feedback Set-Up Time
Synchronous Preset Set-Up
Time
Input Hold Time
External Clock Period (t
CO
+ t
S
)
Clock Width HIGH
[6]
Clock Width LOW
[6]
External Maximum
Frequency (1/(t
CO
+ t
S
))
[11]
Data Path Maximum Frequency
(1/(t
WH
+ t
WL
))
[6, 12]
Internal Feedback Maximum
Frequency (1/(t
CF
+ t
S
))
[6,13]
Register Clock to
Feedback Input
[6,14]
Asynchronous Reset Width
Asynchronous Reset
Recovery Time
Asynchronous Reset to
Registered Output Delay
Synchronous Preset
Recovery Time
Power-Up Reset Time
[6,15]
t
EA
6
8
10
15
25
ns
t
ER
6
8
10
15
25
ns
t
CO
t
S1
t
S2
2
3
4
4
2
5
6
5
2
6
7
7
2
8
2
15
ns
ns
ns
10
10
15
15
t
H
t
P
t
WH
t
WL
f
MAX1
0
7
0
10
3
3
100
0
12
3
3
76.9
0
0
ns
ns
ns
ns
MHz
20
6
6
55.5
30
13
13
33.3
2.5
2.5
143
f
MAX2
200
166
142
83.3
35.7
MHz
f
MAX3
181
133
111
68.9
38.5
MHz
t
CF
2.5
2.5
3
4.5
13
ns
t
AW
t
AR
8
4
8
5
10
6
15
10
25
25
ns
ns
t
AP
7.5
12
13
20
25
ns
t
SPR
4
6
8
10
15
ns
t
PR
Notes:
7.
1
1
1
1
1
μ
s
Part (a) of AC Test Loads and Waveforms is used for all parameters except t
ER
and t
EA(+)
. Part (b) of AC Test Loads and Waveforms is used for t
ER
. Part (c) of AC Test
Loads and Waveforms is used for t
.
Min. times are tested initially and after any design or process changes that may affect these parameters.
The test load of part (a) of AC Test Loads and Waveforms is used for measuring t
. The test load of part (c) of AC Test Loads and Waveforms is used for measuring
t
only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5 volts below V
min. or a previous LOW level has risen to 0.5 volts above V
OL
max. Please see part (e) of AC
Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
internal (1/f
) as measured (see Note above) minus t
.
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure
proper operation, the rise in V
CC
must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied
8.
9.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PALLV16V8-10JC | Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
| PALLV16V8-10PC | Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
| PALLV16V8-10SC | Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
| PAN4820 | On-board type DC Noise Filter for Telecom |
| PAQ65D48 | Dual output DC-DC power module for TELECOM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PALCE22V10_96 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Flash Erasable, Reprogrammable CMOS PAL㈢ Device |
| PALCE22V10-10 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Flash Erasable, Reprogrammable CMOS PAL㈢ Device |
| PALCE22V10-10DMB | 制造商:Cypress Semiconductor 功能描述:SPLD PAL |
| PALCE22V10-10JC | 制造商:Cypress Semiconductor 功能描述:SPLD PAL 制造商:Cypress Semiconductor 功能描述:SPLD PAL? Family 800 Gates 10 Macro Cells 142MHz 5V 28-Pin PLCC |
| PALCE22V10-10JI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Flash-erasable Reprogrammable CMOS PAL Device |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。