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參數(shù)資料
| 型號(hào)： | PALCE22V10 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | PAL |
| 英文描述： | Flash Erasable,Reprogrammable CMOS PAL Device(可擦除閃速，CMOS可重編程PAL器件) |
| 中文描述： | 閃光可擦除，可再編程的CMOS PAL制式設(shè)備（可擦除閃速，可重編程的CMOS器件PAL制式） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 222K |
| 代理商： | PALCE22V10 |
PALCE22V10
2
Functional Description
(continued)
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and provides
up to 22 inputs and 10 outputs. The PALCE22V10 can be elec-
trically erased and reprogrammed. The programmable macro-
cell provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be
specified as
“
registered
”
or
“
combinatorial.
”
Polarity of each
output may also be individually selected, allowing complete
flexibility of output configuration. Further configurability is pro-
vided through
“
array
”
configurable
“
output enable
”
for each po-
tential output. This feature allows the 10 outputs to be recon-
figured as inputs on an individual basis, or alternately used as
a combination I/O controlled by the programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the PALCE
22V10 is optimized to the configurations found in a majority of
applications without creating devices that burden the product
term structures with unusable product terms and lower perfor-
mance.
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, eliminat-
ing the need to dedicate standard product terms for initializa-
tion functions. The device automatically resets upon power-up.
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array com-
plexity. Since each of the 10 output pins may be individually
configured as inputs on a temporary or permanent basis, func-
tions requiring up to 21 inputs and only a single output and
down to 12 inputs and 10 outputs are possible. The 10 poten-
tial outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily en-
abled as an output and an input through the selective use of
individual product terms associated with each output. Each of
these outputs is achieved through an individual programmable
macrocell. These macrocells are programmable to provide a
combinatorial or registered inverting or non-inverting output. In
a registered mode of operation, the output of the register is fed
back into the array, providing current status information to the
array. This information is available for establishing the next re-
sult in applications such as control state machines. In a com-
binatorial configuration, the combinatorial output or, if the out-
put is disabled, the signal present on the I/O pin is made
available to the array. The flexibility provided by both program-
mable product term control of the outputs and variable product
terms allows a significant gain in functional density through the
use of programmable logic.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash re-
programmability.
Selection Guide
Generic Part Number
PALCE22V10-5
PALCE22V10-7
PALCE22V10-10
PALCE22V10-15
PALCE22V10-25
t
PD
ns
t
S
ns
t
CO
ns
I
CC
mA
Com
’
l
5
7.5
10
15
25
Mil/Ind
Com
’
l
3
5
6
10
15
Mil/Ind
Com
’
l
4
5
7
8
15
Mil/Ind
Com
’
l
130
130
90
90
90
Mil/Ind
10
15
25
6
7
8
15
150
120
120
10
15
Configuration Table
Registered/Combinatorial
C
0
0
Registered/Active LOW
1
Registered/Active HIGH
0
Combinatorial/Active LOW
1
Combinatorial/Active HIGH
C
1
0
0
1
1
Configuration
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PALCE22V10_96 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Flash Erasable, Reprogrammable CMOS PAL㈢ Device |
| PALCE22V10-10 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Flash Erasable, Reprogrammable CMOS PAL㈢ Device |
| PALCE22V10-10DMB | 制造商:Cypress Semiconductor 功能描述:SPLD PAL |
| PALCE22V10-10JC | 制造商:Cypress Semiconductor 功能描述:SPLD PAL 制造商:Cypress Semiconductor 功能描述:SPLD PAL? Family 800 Gates 10 Macro Cells 142MHz 5V 28-Pin PLCC |
| PALCE22V10-10JI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Flash-erasable Reprogrammable CMOS PAL Device |
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