參數(shù)資料
型號(hào): PALCE16V8H-5JC/5
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
中文描述: EE PLD, 5 ns, PQCC20
封裝: PLASTIC, LCC-20
文件頁數(shù): 29/32頁
文件大?。?/td> 635K
代理商: PALCE16V8H-5JC/5
6
PALCE16V8 and PALCE16V8Z Families
USE
GAL
DEVICES
FOR
NEW
DESIGNS
Figure 2. Macrocell Congurations
D
Q
OE
CLK
a. Registered active low
D
Q
OE
CLK
b. Registered active high
c. Combinatorial I/O active low
d. Combinatorial I/O active high
e. Combinatorial output active low
VCC
f. Combinatorial output active high
VCC
Adjacent I/O pin
g. Dedicated input
Notes:
1. Feedback is not available on pins 15 and 16 in the
combinatorial output mode.
2. This conguration is not available on pins 15 and 16.
Note 1
Note 2
16493E-2
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