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參數(shù)資料
| 型號(hào)： | PALC22V10-25JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Flash-erasable Reprogrammable CMOS PAL Device |
| 中文描述： | OT PLD, 25 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 5/13頁(yè) |
| 文件大?。?/td> | 367K |
| 代理商： | PALC22V10-25JI |
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PALCE22V10
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03027 Rev. *B
Page 5 of 13
AC Test Loads and Waveforms
R1238
(319
MIL)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
CL
(a)
(b)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5pF
(c)
OUTPUT
CL
R1238
(319
MIL)
R2170
(236
MIL)
R2170
(236
MIL)
750
(1.2K
MIL)
OUTPUT
2.08V = V
THC
OUTPUT
2.13V = V
THM
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
< 2ns
< 2ns
(d)
99
136
Equivalent to:THé VENIN Equivalent (Commercial)
Equivalent to: THé VENIN Equivalent (Military)
Load Speed
5, 7.5, 10, 15, 25 ns
C
L
50 pF
Package
PDIP, CDIP,
PLCC, LCC
Commercial Switching Characteristics PALCE22V10
[2, 7]
Parameter
t
PD
Description
22V10-5
Min.
3
22V10-7
Min.
3
22V10-10
Min.
3
22V10-15
Min.
3
22V10-25
Min.
3
Unit
ns
Max.
5
Max.
7.5
Max.
10
Max.
15
Max.
25
Input to Output
Propagation Delay
[8]
Input to Output Enable Delay
[9]
Input to Output Disable Delay
[10]
Clock to Output Delay
[8]
t
EA
t
ER
t
CO
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters except t
ER
and t
EA(+)
. Part (b) of AC Test Loads and Waveforms is used for t
ER
. Part (c) of AC Test
Loads and Waveforms is used for t
.
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. The test load of (a) of AC Test Loads and Waveforms is used for measuring t
. The test load of (c) of AC Test Loads and Waveforms is used for measuring t
EA(+)
only.
Please see (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
10.This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5V below V
min. or a previous LOW level has risen to 0.5V above V
OL
max. Please see (e) of AC Test Loads
and Waveforms for enable and disable test waveforms and measurement reference levels.
6
6
4
8
8
5
10
10
7
15
15
8
25
25
15
ns
ns
ns
2
2
2
2
2
Parameter
V
X
1.5V
Output Waveform Measurement Level
t
ER (- )
V
OH
0.5V
V
X
0.5V
t
ER (+)
2.6V
V
OL
V
X
t
EA (+)
0V
0.5V
t
EA (- )
V
thc
V
X
V
OL
1.5V
V
X
V
OH
(e) Test Waveforms
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PALC22V10-25KMB | 制造商:Rochester Electronics LLC 功能描述:PLD - Bulk |
| PALC22V1025PC | 制造商:CYP 功能描述:22V10-25 CYP'95 |
| PALC22V10-25PC | 功能描述:IC SPLD 10MACROCELL 25NS 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - PLD（可編程邏輯器件） 系列:- 標(biāo)準(zhǔn)包裝:46 系列:- 可編程類型:PAL FLASH 宏單元數(shù):8 輸入電壓:5V 速度:15ns 安裝類型:表面貼裝 封裝/外殼:20-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:20-PLCC（9x9） 包裝:管件 其它名稱:428-1277 |
| PALC22V10-25PI | 制造商:Cypress Semiconductor 功能描述:SPLD PAL |
| PALC22V10-25WC | 制造商:Cypress Semiconductor 功能描述:SPLD PAL? Family 10 Macro Cells 5V 24-Pin Windowed CDIP 制造商:Cypress Semiconductor 功能描述:Simple EPLD, Programmable Array Logic, 24 Pin, Ceramic, DIP |
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