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參數(shù)資料
| 型號： | PAC-POWR1208 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | ispPAC-POWR1208 Evaluation Board |
| 中文描述： | 可編程模擬器- POWR1208評估板 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 992K |
| 代理商： | PAC-POWR1208 |
ispPAC-POWR1208 Evaluation Board
PAC-POWR1208-EV
Lattice Semiconductor
3
On the evaluation board, VDD and VDDINP are normally connected together with a user-removable jumper (J7.5).
This jumper can be removed to allow for independent VDD and VDDINP supplies.
Input/Output Connections
Connectors are provided for key functions and test points on this evaluation board, as shown In Figure 3. Power is
supplied through two color coded (RED = +, BLACK = -) banana jacks in the upper right corner of the board.
The JTAG programming cable is connected to a keyed header (P1) in the lower right corner of the board. A PCB
land pattern is provided for the addition of an additional JTAG interface header (P2) to allow for connecting multiple
PAC-POWR1208-EV evaluation boards into a multi-device programming chain.
Access to the ispPAC-POWR1208’s I/O pins is available at P5, which is a 2x20 row of pads to which one may
attach test probes or a ribbon-cable connector. At this point all of the device’s I/O pins (except those required for
the JTAG programming interface) are accessible.
Figure 3. I/O and Jumpers
Jumper Options
Several jumpers are provided on the evaluation board to make it simple to implement common circuit con
fi
gura-
tions. These jumpers are:
J7
enable the pull-ups on an output-by-output basis. The pull-up voltage is selected by J8. Position 5 (the right-
most position) is used to connect VDDINP to VDD, and should normally be left in place. This jumpers needs
to be removed when using separate VDD and VDDINP supplies.
J8
- Selects a pull-up voltage to which the High-Voltage outputs (HVOUT1-4) may be pulled up to, either
VDD or VDDINP.
J9
- Selects whether open-drain digital outputs OUT5-OUT8 are pulled up to VDD (upper position), VDDINP
(lower position), or not pulled up at all. These outputs are pulled up through 2K
- positions 1-4 connect pull-up resistors to the high voltage outputs HVOUT1-4, and allow the user to
resistors.
1
P1
JTAG Interface
VDD
GND
VMON1
VMON3
J9
J8
J7
1 2 3 4
VDD
VDDINP
VDD
HVOUT[1-4]
VDDINP
VDD
VDDINP
OUT[5-8]
HVOUT
PULL-UP
ispPAC-
POWR1208
OUT8
OUT7
OUT6
OUT5
Power
TDO
RESET
VMON2
VMON4
VDD
IN2
IN4
VMON11
HVOUT4
HVOUT2
VMON9
VMON7
VMON12
HVOUT3
HVOUT1
IN1
IN3
RESET
GND
GND
OUT6
OUT8
COMP7
COMP5
COMP3
COMP1
CLK
VMON10
VMON8
VMON6
VMON5
VDDINP
GND
OUT5
OUT7
COMP8
COMP6
COMP4
COMP2
POR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PACPOWR1208-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 PAC1208 Eval Board RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| PACPOWR1208P1-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 PAC1208P1 Eval Board RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| PAC-POWR1220AT8-HA-EVN | 功能描述:電源管理IC開發(fā)工具 Pwr Manager Hercules Advanced Dev Kit RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| PAC-POWR1220AT8-HS-EVN | 功能描述:電源管理IC開發(fā)工具 Pwr Mgr Hercules Std Development Kit RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| PACPOWR605-P-EVN | 功能描述:電源管理IC開發(fā)工具 POWR605 EVAL BRD Processor RPM RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
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