參數(shù)資料
型號: PAC-POWR1208
廠商: Lattice Semiconductor Corporation
英文描述: ispPAC-POWR1208 Evaluation Board
中文描述: 可編程模擬器- POWR1208評估板
文件頁數(shù): 1/6頁
文件大?。?/td> 992K
代理商: PAC-POWR1208
www.latticesemi.com
1
an6040_01
ispPAC-POWR1208 Evaluation Board
PAC-POWR1208-EV
April 2004
Application Note AN6040
Introduction
The Lattice Semiconductor ispPAC
-POWR1208 In-System-Programmable Analog Circuit allows designers to
implement both the analog and digital functions of a power supply monitoring and sequencing subsystem within a
single integrated circuit. By integrating analog functions such as comparators and programmable slew rate FET
drivers with the digital functionality of a Programmable Logic Device (PLD), the ispPAC-POWR1208 provides the
power-supply designer with a rich set of features in a single device.
ISP (In-System-Programmability) provides the designer with an unprecedented level of
fl
exibility, allowing him to
con
fi
gure analog parameters such as threshold voltages as well as de
fi
ning state machines and combinatorial logic
functions. All con
fi
guration data is stored internally in E
2
CMOS
nonvolatile memory. Programming a con
fi
guration
is accomplished through an industry-standard JTAG IEEE 1149.1 interface.
PAC-POWR1208-EV Evaluation Board
The PAC-POWR1208-EV evaluation board (Figure 1) allows the designer to quickly con
fi
gure and evaluate the isp-
PAC-POWR1208 on a fully assembled printed-circuit board. The double-sided board supports a 44-pin TQFP pack-
age, a header for user I/O, a JTAG programming cable connector, and an uncommitted pad array for user
prototyping. JTAG programming signals can be generated by using an ispDOWNLOAD
programming cable con-
nected between the evaluation board and a PC’s parallel (printer) port. Both analog and digital features of the isp-
PAC-POWR1208 can be easily con
fi
gured using PAC-Designer
software.
Figure 1. PAC-POWR1208-EV Evaluation Board
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