參數(shù)資料
型號(hào): PA7540S-15
英文描述: PA7540 PEEL Array? Programmable Electrically Erasable Logic Array
中文描述: PA7540果皮陣列?電可擦除可編程邏輯陣列
文件頁(yè)數(shù): 8/10頁(yè)
文件大?。?/td> 239K
代理商: PA7540S-15
8
04-02-051B
Table 5. A.C. Electrical Characteristics Sequential
-15/I-15
Min
6
Symbol
Parameter
6,1
Max
8
12
6
7
71.4
62.5
55.5
50.0
71.4
1
12
6
1
7
5
Unit
t
SCI
t
SCX
t
COI
t
COX
t
HX
t
SK
t
AK
t
HK
t
SI
t
HI
t
PK
t
SPI
t
HPI
t
CK
t
CW
f
MAX1
f
MAX2
f
MAX3
f
MAX4
f
TGL
t
PR
t
ST
t
AW
t
RT
t
RTV
t
RTC
t
RW
t
RESET
Internal set-up to system clock
8
- LCC
14
(t
AL
+ t
SK
+ t
LC
- t
CK
)
Input
16
(EXT.) set-up to system clock, - LCC (t
IA
+ t
SCI
)
System-clock to Array Int. - LCC/IOC/INC
14
(t
CK
+t
LC
)
System-clock to Output Ext. - LCC (t
COI
+ t
LO
)
Input hold time from system clock - LCC
LCC Input set-up to async. clock
13
- LCC
Clock at LCC or IOC - LCC output
LCC input hold time from system clock - LCC
Input set-up to system clock - IOC/INC
14
(t
SK
- t
CK
)
Input hold time from system clock - IOC/INC (t
SK
- t
CK
)
Array input to IOC PCLK clock
Input set-up to PCLK clock
17
- IOC/INC (t
SK
-t
PK
-t
IA
)
Input hold from PCLK clock
17
- IOC/INC (t
PK
+t
IA
-t
SK
)
System-clock delay to LCC/IOC/INC
System-clock low or high pulse width
Max. system-clock frequency Int/Int 1/(t
SCI
+ t
COI
)
Max. system-clock frequency Ext/Int 1/(t
SCX
+ t
COI
)
Max. system-clock frequency Int/Ext 1/(t
SCI
+ t
COX
)
Max. system-clock frequency Ext/Ext 1/(t
SCX
+ t
COX
)
Max. system-clock toggle frequency 1/(t
CW
+ t
CW
)
9
LCC presents/reset to LCC output
Input to Global Cell present/reset (t
IA
+ t
AL
+ t
PR
)
Asynch. preset/reset pulse width
Input to LCC Reg-Type (RT)
LCC Reg-Type to LCC output register change
Input to Global Cell register-type change (t
RT
+ t
RTV
)
Asynch. Reg-Type pulse width
Power-on reset time for registers in clear state
2
ns
8
0
3
1
4
0
4
0
5
7
8
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
μs
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