參數(shù)資料
型號(hào): PA28F002BC-T120
廠商: INTEL CORP
元件分類(lèi): PROM
英文描述: 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY
中文描述: 256K X 8 FLASH 12V PROM, 120 ns, PDSO44
封裝: 0.525 X 1.110 INCH, PLASTIC, SOP-44
文件頁(yè)數(shù): 20/37頁(yè)
文件大?。?/td> 455K
代理商: PA28F002BC-T120
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
20
PRELIMINARY
SR.7 = 1
No
Yes
Start
Write 40H and
Byte Address
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read
Status Register
V Range Error
Bus
Operation
Command
Comments
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.4 is only cleared by the Clear Status Register command, in cases
where multiple bytes are programmed before full status is checked.
If error is detected, clear the status register before attempting retry
or other error recovery.
Bus
Operation
Command
Comments
Write
Write
Program
Setup
Data = Data to Program
Addr = Location to Program
Read
Data = 40H
Addr = Byte to Program
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
SR.3 =
SR.4 =
Program Error
Program Successful
Check SR.4
1 = Program Error
Check SR.3
1 = V Low Detect
Program
Status Register Data
Toggle CE# or OE# to Update SRD.
Write Data and
Data Address
Repeat for subsequent writes.
SR Full Status Check can be done after each write, or after
a sequence of writes.
Write FFH after the last write operation to reset device to
read array mode.
0578_06
Figure 7. Automated Programming Flowchart
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