參數(shù)資料
型號(hào)： P8xCL580HFT
廠商： NXP Semiconductors N.V.
英文描述： Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
中文描述： 低電壓8 - UART的，位微控制器的I2C總線和ADC
文件頁數(shù)： 55/80頁
文件大?。?/td> 366K
代理商： P8XCL580HFT
1997 Mar 14
55
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I
2
C-bus and ADC
P80CL580; P83CL580
19 RESET
To initialize the P8xCL580 a reset is performed by either of
three methods:
Applying an external signal to the RST pin
Via Power-on-reset circuitry
Watchdog Timer.
A reset leaves the internal registers as shown in
Chapter 20. The reset state of the port pins is
mask-programmable and can be defined by the user.
19.1
External reset using the RST pin
The reset input for the P8xCL580 is RST. A Schmitt trigger
is used at the input for noise rejection. The output of the
Schmitt trigger is sampled by the reset circuitry every
machine cycle. A reset is accomplished by holding the
RST pin HIGH for at least two machine cycles
(24 oscillator periods) while the oscillator is running.
The CPU responds by executing an internal reset. Port
pins adopt their reset state immediately after the RST goes
HIGH. During reset, ALE and PSEN are held HIGH.
The external reset is asynchronous to the internal clock.
The RST pin is sampled during state 5, phase 2 of every
machine cycle. After a HIGH is detected at the RST pin, an
internal reset is repeated until RST goes LOW. The reset
circuitry is also affected by the Watchdog timer; see
Section 11.4. The internal RAM is not affected by reset.
When V
DD
is turned on, the RAM contents are
indeterminate.
19.2
Power-on-reset
The device contains on-chip circuitry which switches the
port pins to the customer defined logic level as soon as
V
DD
exceeds 1.3 V; if the mask option ‘ON’ has been
chosen. As soon as the minimum supply voltage is
reached, the oscillator will start up. However, to ensure
that the oscillator is stable before the controller starts, the
clock signals are gated away from the CPU for a further
1536 oscillator periods. During that time the CPU is held in
a reset state. A hysteresis of approximately 50 mV at a
typical power-on switching level of 1.3 V will ensure
correct operation (see Fig.35).
The on-chip Power-on reset circuitry can also be switched
off via the mask option ‘OFF’. This option reduces the
Power-down current to typically 800 nA and can be
chosen if external reset circuitry is used. For applications
not requiring the internal reset, option ‘OFF’ should be
chosen.
An automatic reset can be obtained by connecting the RST
pin to V
DD
via a 10
μ
F capacitor. At power-on, the voltage
on the RST pin is equal to V
DD
minus the capacitor voltage,
and decreases from V
DD
as the capacitor charges through
the internal resistor (R
RST
) to ground. The larger the
capacitor, the more slowly V
RST
decreases. V
RST
must
remain above the lower threshold of the Schmitt trigger
long enough to effect a complete reset. The time required
is the oscillator start-up time, plus 2 machine cycles.
The Power-on-reset circuitry is shown in Fig.34.
Fig.33 Reset configuration.
handbook, halfpage
MGC757
SCHMITT
TRIGGER
RESET
CIRCUITRY
RST
P
T3 overflow
POR
RRST
VDD
Fig.34 Recommended Power-on-reset circuitry.
handbook, halfpage
MGC760
P80CL580
P83CL580
10
μ
F
RRST
RST
VDD
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