1997 Mar 14
26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I
2
C-bus and ADC
P80CL580; P83CL580
14.4
Status of external pins
The status of the external pins during Idle and Power-down
mode is shown in Table 13. If the Power-down mode is
activated whilst accessing external Program Memory, the
port data that is held in the Special Function Register P2 is
restored to Port 2.
If the data is a logic 1, the port pin is held HIGH during the
Power-down mode by the strong pull-up transistor ‘p1’;
see Fig.9(a).
Table 13
Status of external pins during Idle and Power-down modes
14.5
Power Control Register (PCON)
Idle and Power-down modes are activated by software using this SFR. PCON is not bit addressable, the reset value of
PCON is 0XX00000B.
Table 14
Power Control Register (address 87H)
Table 15
Description of PCON bits
MODE
MEMORY
ALE
PSEN
PWM0
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
Idle
internal
external
internal
external
1
1
0
0
1
1
0
0
active
active
HIGH
HIGH
port data
floating
port data
floating
port data
port data
port data
port data
port data
address
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
Power-down
7
6
4
3
2
1
0
SMOD
WLE
GF1
GF0
PD
IDL
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double Baud rate bit
. When set to a logic 1 the baud rate is doubled when the serial
port SIO0 is being used in modes 1, 2 or 3.
Reserved.
Watchdog Load Enable
. This flag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when T3 is loaded.
GF1 and GF0
General purpose flag bits
.
PD
Power-down bit
. Setting this bit activates the Power-down mode. This bit can only be
set if input EWN is HIGH. If a logic 1 is written to both PD and IDL at the same time, PD
takes precedence.
IDL
Idle mode bit
. Setting this bit activates the Idle mode.
6 and 5
4
WLE
3 and 2
1
0