參數(shù)資料
型號(hào)： P8XC151SA
廠商： Intel Corp.
英文描述： HIGH-PERFORMANCE CHMOS MICROCONTROLLER
中文描述： 高性能CHMOS單片機(jī)
文件頁(yè)數(shù)： 29/33頁(yè)
文件大?。?/td> 312K
代理商： P8XC151SA
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 12. Programming and Verification Modes Mode
8XC151SA/SB
Addresses
P1 (high), P3 (low)
Mode
PROG
Y
P0
P2
Notes
X
e
7
X
e
3
Program On-Chip Code
Memory
Y
5 Pulses
68H
Data
0000H–3FFFH (16K)
0000H–1FFFH (8K)
1
Verify On-Chip Code
Memory
Y
Y
High
28H
Data
0000H–3FFFH (16K)
0000H–1FFFH (8K)
Program Configuration
Bytes
2
Verify Configuration
Bytes
2
Program Lock Bits
Y
25 Pulses
6BH
XX
0001H–0003H
1, 3
Verify Lock Bits
Y
Y
High
2BH
Data
0000H
4
Program Encryption
Array
Y
25 Pulses
6CH
Data
0000H–007FH
1
Verify Signature Bytes
Y
Y
High
29H
Data
0030H, 0031H, 0060H
NOTES:
1. The PROG
Y
pulse waveform is shown in Figure 19.
2. Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a
separate hexadecimal disk file. 8XC151SA/SB devices without internal ROM/OTPROM arrays fetch configuration byte
information from external application memory based on an internal address range of FFF9:8H.
3. When programming the lock bits, the data bits on port 2 are don’t care. Identify the lock bits with the address as follows:
LB3 - 0003H, LB2 - 0002H, LB1 - 0001H.
4. The three lock bits are verified in a single operation. The states of the lock bits appear simultaneously at port 2 as
follows: LB3 - P2.3, LB2 - P2.2. LB1 - P2.1. High
e
programmed.
29
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