參數(shù)資料
型號(hào): P89V51RC2FN,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 39/80頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 40-DIP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 9
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱(chēng): 568-2430-5
935278782112
P89V51RC2FN
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
44 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
2
CPHA
Clock Phase control bit. 1 = shift triggered on the trailing edge of the
clock; 0 = shift triggered on the leading edge of the clock.
1
SPR1
SPI Clock Rate Select bit 1. Along with SPR0 controls the SPICLK
rate of the device when a master. SPR1 and SPR0 have no effect on
the slave. See Table 30 below.
0
SPR0
SPI Clock Rate Select bit 0. Along with SPR1 controls the SPICLK
rate of the device when a master. SPR1 and SPR0 have no effect on
the slave. See Table 30 below.
Table 30.
SPCR - SPI control register (address D5H) clock rate selection
SPR1
SPR0
SPICLK = fosc divided by
00
4
01
16
10
64
1
128
Table 31.
SPSR - SPI status register (address AAH) bit allocation
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Bit
7
6
5
4
3
2
1
0
Symbol
SPIF
WCOL
-
Table 32.
SPSR - SPI status register (address AAH) bit description
Bit
Symbol
Description
7
SPIF
SPI interrupt ag. Upon completion of data transfer, this bit is set to ‘1’.
If SPIE = 1 and ES = 1, an interrupt is then generated. This bit is
cleared by software.
6
WCOL
Write Collision Flag. Set if the SPI data register is written to during
data transfer. This bit is cleared by software.
5 to 0
-
Reserved for future use. Should be set to ‘0’ by user programs.
Table 29.
SPCR - SPI control register (address D5H) bit description …continued
Bit
Symbol
Description
Fig 18. SPI transfer format with CPHA = 0
002aaa529
SPICLK cycle #
(for reference)
SPICLK (CPOL = 0)
SPICLK (CPOL = 1)
MOSI
(from master)
MISO
(from slave)
SS (to slave)
12
3
4
5
6
7
8
MSB
6543
2
1
LSB
MSB
6543
2
1
LSB
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