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參數(shù)資料
| 型號(hào)： | P89V51RC2FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 6/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 32K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-2429 935277725557 P89V51RC2FBC |
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P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
14 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.2 Memory organization
The device has separate address spaces for program and data memory.
6.2.1 Flash program memory bank selection
There are two internal ash memory blocks in the device. Block 0 has 16/32/64 kB and is
organized as 128/256/512 sectors, each sector consists of 128 B. Block 1 contains the
IAP/ISP routines and may be enabled such that it overlays the rst 8 kB of the user code
memory. The overlay function is controlled by the combination of the Software Reset Bit
(SWR) at FCF.1 and the Bank Select Bit (BSEL) at FCF.0. The combination of these bits
and the memory source used for instructions is shown in Table 5.
Access to the IAP routines in block 1 may be enabled by clearing the BSEL bit (FCF.0),
provided that the SWR bit (FCF.1) is cleared. Following a power-on sequence, the boot
code is automatically executed and attempts to autobaud to a host. If no autobaud occurs
within approximately 400 ms and the SoftICE ag is not set, control will be passed to the
user code. A software reset is used to accomplish this control transfer and as a result the
SWR bit will remain set. Therefore the user's code will need to clear the SWR bit in
order to access the IAP routines in block 1. However, caution must be taken when
dynamically changing the BSEL bit. Since this will cause different physical memory to be
mapped to the logical program address space, the user must avoid clearing the BSEL bit
when executing user code within the address range 0000H to 1FFFH.
6.2.2 Power-on reset code execution
At initial power up, the port pins will be in a random state until the oscillator has started
and the internal reset algorithm has weakly pulled all pins high. Powering up the device
without a valid reset could cause the MCU to start executing instructions from an
indeterminate location. Such undened states may inadvertently corrupt the code in the
ash. A system reset will not affect the 1 kB of on-chip RAM while the device is running,
however, the contents of the on-chip RAM during power up are indeterminate.
When power is applied to the device, the RST pin must be held high long enough for the
oscillator to start up (usually several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An example of a method to extend the
RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 F
circuit is being used, provisions should be made to ensure the VDD rise time does not
exceed 1 ms and the oscillator start-up time does not exceed 10 ms.
For a low frequency oscillator with slow start-up time the reset signal must be extended in
order to account for the slow start-up time. This method maintains the necessary
relationship between VDD and RST to avoid programming at an indeterminate location,
which may cause corruption in the code of the ash. The power-on detection is designed
Table 5.
Code memory bank selection
SWR (FCF.1)
BSEL (FCF.0)
Addresses from 0000H to
1FFFH
Addresses above 1FFFH
0
boot code (in block 1)
user code (in block 0)
0
1
user code (in block 0)
10
11
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| P89V51RC2FN | 制造商:NXP Semiconductors 功能描述:IC MCU 8BIT 80C51 32K FLASH DIP40 |
| P89V51RC2FN,112 | 功能描述:8位微控制器 -MCU 80C51 32K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89V51RC2FN112 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 40MHZ DIP-40 |
| P89V51RD2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 64 kB Flash microcontroller with 1 kB RAM |
| P89V51RD2BN | 制造商:NXP Semiconductors 功能描述:IC MCU 8BIT 80C51 64K FLASH DIP40 制造商:NXP Semiconductors 功能描述:IC, MCU 8BIT 80C51 64K FLASH, DIP40 |
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