參數(shù)資料
型號(hào): P89V51RB2BA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù): 60/77頁
文件大小: 350K
代理商: P89V51RB2BA
Philips Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Product data
Rev. 03 — 02 December 2004
60 of 77
9397 750 14341
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.12 System clock and clock options
7.12.1
Clock Input Options and Recommended Capacitor Values for Oscillator
Shown in
Figure 28
are the input and output of an internal inverting amplifier (XTAL1,
XTAL2), which can be configured for use as an on-chip oscillator.
When driving the device from an external clock source, XTAL2 should be left
disconnected and XTAL1 should be driven.
At start-up, the external oscillator may encounter a higher capacitive load at XTAL1
due to interaction between the amplifier and its feedback capacitance. However, the
capacitance will not exceed 15 pF once the external signal meets the V
IL
and V
IH
specifications.
Crystal manufacturer, supply voltage, and other factors may cause circuit
performance to differ from one application to another. C1 and C2 should be adjusted
appropriately for each design.
Table 59
shows the typical values for C1 and C2 vs.
crystal type for various frequencies
More specific information about on-chip oscillator design can be found in the
FlashFlex51 Oscillator Circuit Design Considerationsapplication note.
Table 58:
Mode
Idle Mode
Power-saving modes
Initiated by
Software
(Set IDL bit in PCON)
MOV PCON, #01H;
State of MCU
CLK is running.
Interrupts, serial port and
timers/counters are active.
Program Counter is stopped.
ALE and PSEN signals at a
HIGH level during Idle. All
registers remain unchanged.
Exited by
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits idle mode,
after the ISR RETI instruction, program
resumes execution beginning at the
instruction following the one that invoked
idle mode. A user could consider placing
two or three NOP instructions after the
instruction that invokes idle mode to
eliminate any problems. A hardware reset
restarts the device similar to a power-on
reset.
Enabled external level sensitive interrupt or
hardware reset. Start of interrupt clears PD
bit and exits Power-down mode, after the
ISR RETI instruction program resumes
execution beginning at the instruction
following the one that invoked Power-down
mode. A user could consider placing two or
three NOP instructions after the instruction
that invokes Power-down mode to eliminate
any problems. A hardware reset restarts the
device similar to a power-on reset.
Power-down
Mode
Software
(Set PD bit in PCON)
MOV PCON, #02H;
CLK is stopped. On-chip SRAM
and SFR data is maintained.
ALE and PSEN signals at a
LOW level during power -down.
External Interrupts are only
active for level sensitive
interrupts, if enabled.
Table 59:
Crystal
Quartz
Ceramic
Recommended values for C1 and C2 by crystal type
C1 = C2
20 pF to 30 pF
40 pF to 50 pF
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