參數(shù)資料
型號(hào): P89V51RB2BA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁(yè)數(shù): 43/77頁(yè)
文件大?。?/td> 350K
代理商: P89V51RB2BA
Philips Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Product data
Rev. 03 — 02 December 2004
43 of 77
9397 750 14341
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Fig 17. SPI master-slave interconnection.
002aaa528
8-bit Shift Register
MSB Master LSB
SPI
Clock Generator
MISO
MISO
MOSI
MOSI
SCK
SCK
SS
SS
8-bit Shift Register
MSB Slave LSB
VSS
VDD
Table 30:
Bit addressable; Reset source(s): any reset; Reset value: 00000000B
Bit
7
6
Symbol
SPIE
SPE
DORD
SPCR - SPI control register (address D5H) bit allocation
5
4
3
2
1
0
MSTR
CPOL
CPHA
SPR1
SPR0
Table 31:
Bit
7
6
5
SPCR - SPI control register (address D5H) bit description
Symbol
Description
SPIE
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPE
SPI enable bit. When set enables SPI.
DORD
Data transmission order. 0 = MSB first; 1 = LSB first in data
transmission.
MSTR
Master/slave select. 1 = master mode, 0 = slave mode.
CPOL
Clock polarity. 1 = SCK is high when idle (active LOW), 0 = SCK is
low when idle (active HIGH).
CPHA
Clock Phase control bit. 1 = shift triggered on the trailing edge of
the clock; 0 = shift triggered on the leading edge of the clock.
SPR1
SPI Clock Rate Select bit 1. Along with SPR0 controls the SCK
rate of the device when a master. SPR1 and SPR0 have no effect
on the slave. See
Table 32
below.
SPR0
SPI Clock Rate Select bit 0. Along with SPR1 controls the SCK
rate of the device when a master. SPR1 and SPR0 have no effect
on the slave. See
Table 32
below.
4
3
2
1
0
Table 32:
SPR1
0
0
1
1
SPCR - SPI control register (address D5H) clock rate selection
SPR0
0
1
0
1
SCK = f
osc
divided by
4
16
64
128
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