參數(shù)資料
型號(hào): P89LV51RD2BA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
中文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁(yè)數(shù): 46/77頁(yè)
文件大?。?/td> 349K
代理商: P89LV51RD2BA
Philips Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Product data
Rev. 04 — 02 December 2004
46 of 77
9397 750 14342
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.8 Programmable Counter Array (PCA)
The PCA includes a special 16-bit Timer that has five 16-bit capture/compare
modules associated with it. Each of the modules can be programmed to operate in
one of four modes: rising and/or falling edge capture, software timer, high-speed
output, or pulse width modulator. Each module has a pin associated with it in port 1.
Module 0 is connected to P1.3 (CEX0), module 1 to P1.4 (CEX1), etc. Registers CH
and CL contain current value of the free running up counting 16-bit PCA timer. The
PCA timer is a common time base for all five modules and can be programmed to run
at:
1
6
the oscillator frequency,
1
2
the oscillator frequency, the Timer 0 overflow, or the
input on the ECI pin (P1.2). The timer count source is determined from the CPS1 and
CPS0 bits in the CMOD SFR (see
Table 37
and
Table 38
).
In the CMOD SFR there are three additional bits associated with the PCA. They are
CIDL which allows the PCA to stop during idle mode, WDTE which enables or
disables the Watchdog function on module 4, and ECF which when set causes an
interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows.
Table 36:
Bit
7 to 5
4
WDTC - Watchdog control register (address COH) bit description
Symbol
Description
-
Reserved for future use. Should be set to
‘0’
by user programs.
WDOUT
Watchdog output enable. When this bit and WDRE are both set, a
Watchdog reset will drive the reset pin active for 32 clocks.
WDRE
Watchdog timer reset enable. When set enables a Watchdog timer
reset.
WDTS
Watchdog timer reset flag, when set indicates that a WDT reset
occurred. Reset in software.
WDT
Watchdog timer refresh. Set by software to force a WDT reset.
SWDT
Start Watchdog timer, when set starts the WDT. When cleared,
stops the WDT.
3
2
1
0
Fig 21.
002aaa532
PCA TIMER/COUNTER
time base for PCA modules
MODULE0
16 bits
16 bits
P1.3/CEX0
MODULE1
P1.4/CEX1
MODULE2
P1.5/CEX2
MODULE3
P1.6/CEX3
MODULE4
P1.7/CEX4
Module functions:
16-bit capture
16-bit timer
16-bit high speed output
8-bit PWM
Watchdog timer (Module 4 only)
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