參數(shù)資料
型號(hào)： P89LPC954FBD48,151
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 20/69頁(yè)
文件大?。?/td> 0K
描述： IC 80C51 MCU 16KB FLASH 48LQFP
標(biāo)準(zhǔn)包裝： 250
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-LQFP
包裝： 托盤
其它名稱： 568-8736
P89LPC954FBD48,151-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
27 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, IP1H, IP2, and
IP2H. An interrupt service routine in progress can be interrupted by a higher priority
interrupt, but not by another interrupt of the same or lower priority. The highest priority
interrupt service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
7.12.1 External interrupt inputs
The P89LPC952/954 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard 80C51
microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request ag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC952/954 is put into Power-down or Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
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